3 Misconceptions About RISC You Shouldn’t Believe

When I started to study computer science in the 2000s, I learned about the two types of processor architectures: RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer).

At that time, the message was pretty clear: RISC is the right opposite of CISC. The former is simple, tiny, lean, while the latter is complex, big, bloated.

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I have been carrying this idea for many years since then. But, when I decided to write an article about the increasing adoption of RISC processors in HPC (High Performance Computing), I realized how much outdated I was about this topic.

Instead of proceeding with the original idea, I wondered: why not writing a post to share my own misleading about RISC? It will clarify other persons who, like me, have the same misconception on this issue.

So, here we are! I brought four fallacies involving RISC (and CISC) processors.

1. RISC is synonym of fewer instructions

This assertion is not necessarily true. Modern RISC processors targeted to high computationally workloads can have larger ISAs, trespassing thousands of instructions.

For example, a RISC processor compliant with ARMv9-A, such as Google Axion and AWS Graviton, can have more than 2000 instructions, distributed among the base AArch64 instruction set and extensions like SVE2, MTE and NEON.

AWS Graviton can have more than 2000 instructions. Credit:

In the other hand, a processor based in the ARMv6-M specification, like the low energy microcontroller Cortex-M0, does not exceed the number of 100 unique instructions1, approximately.

In a broader sense, we should no longer associate RISC processors to the idea of a smaller ISA. We must leave this old definition in the past.

Ok, but if the number of instructions is no more suitable to classify an architecture as RISC or CISC, then what would be the criteria to distinguish between them?

Fixed-size Instructions

Among other aspects, RISC architectures usually have fixed-size instructions, whereas CISC architectures commonly have instructions of variable lengths.

For example, the whole set of instructions specified in ARMv9 have a fixed-size of 32 bits. No matter the instruction’s purpose (logical, arithmetic, flow control) or addressing mode (register, PC-relative, base-displacement), all instructions have the same 4 bytes of size.

But instructions specified in x86_64 have lengths varying from 1 to 15 bytes. For instance, instructions “NOP” and “ADD EBX, 0x1234” have sizes of 1 and 6 bytes, respectively.

Why does it matter? Instructions of fixed-size are faster to decode and execute.

By dealing with instructions of constant length, the processor does not need to waste clock cycles and resources to determine where the current instruction ends and the next one begins.

Conclusion

The term “Reduced” in RISC acronym does not relate to the number of instructions supported by the processor, but to the simplicity of instructions.

2. RISC is faster than CISC

At the 1990s, RISC processors were used to empower workstations and supercomputers.

Indeed, the Sun SuperSPARC CPU, a RISC-based processor, endowed the world’s fastest machine in 1993 (first position in Top500).

Nowadays, modern high-performance CISC-based CPUs like Intel’s Xeon and AMD’s Epyc series deliver extreme performance for a plethora of workloads.

These processors achieve such performance because the strategy of translating complex instructions into RISC-like instructions called micro-operations.

Micro-operations

A micro-operation is nothing more than a simpler instruction, usually executed in a few cycles, and designed to perform a basic task or operation.

For example, the instruction DIV(M64)2, when executed in Intel’s Emerald Rapids processors family, is decomposed into four micro-operations:

1. mov
2. movabs
3. div
4. lfence

In fact, these micro-operations are simply instructions. As such, the processor can take advantage of the parallelism present in the pipeline to execute these instructions in a more efficient manner.

In general, modern CISC processors adopt an hybrid approach. They are not purely CISC, so to say.

Among other aspects, the strategy of decomposing a complex instruction into a few simpler and faster instructions is one of the reasons for bursting the performance of CISC processors.

So, if CISC can be faster than RISC, what is the deal of using the latter?

It’s a fair question and the answer is straightforward: energy efficiency. But let’s this topic to explore in another post.

Conclusion

In general, RISC used to be faster than CISC in the past four or three decades.

Today, with the RISC-like micro-operations implemented in CISC, we cannot say that a given processor is faster than others just because of its architecture type.

3. RISC is now coming back from the shadows

At some time in the early 1990s, CISC displaced RISC in the niche of workstations and computing servers.

From that point on, x86_64 processors, mostly from Intel and AMD, have dominated the industry of laptops, desktops, workstations, servers, and supercomputers.

More than 30 years after RISC displacement, we started to hear more frequently about this architecture in the mainstream media.

In 2021, for example, RISC appeared in the first position of Top500. The supercomputer Fugaku achieved 1 Exaflop of computing power by using an ARM-based CPU, the Fujitsu A64FX processor.

These days, we periodically see news about novel ARM and RISC-V based processors focused in HPC, AI, and general computing. Many of them available at cloud services.

To some extent, we may wrongly conclude that RISC was left in the shadows for the last 3 decades. But this is not true. It turns out that after displacement in workstations and servers, RISC has shifted to the niche of embedded devices.

RISC is in Everything

The adoption of RISC processors in embedded devices gained traction in the 1990s, when vendors spread MIPS processors in printers, routers, switches, handheld PCs, and PDAs.

But it was in the 2010s that RISC consolidated its dominance in this area because of the massive usage of mobile devices.

Currently, RISC is the de facto architecture adopted in all sort of embedded devices due to its incredible versatility and low power consumption.

We find RISC-based processors in smartphones, wearables, IoT devices, smart home appliances, consumer electronics, and more.

Even so, it seems that RISC is coming back to the high performance golden age. But this is a topic for another talk.

Conclusion

RISC never left the scene. It was always around us.

It turns out that people do not care about the kind of processor used in a smartwatch or television. So, despite RISC being widely adopted in many devices for all these years, it did not receive the same attention of CISC processors.

As a result, many of us fall in the fallacy that RISC was forgotten in the past. We are completely wrong.

Originally published at theparallelminds.substack.com