Designing a Vending Machine Using an FSM (Finite State Machine) in Verilog

Ever wondered what really happens inside a vending machine when you drop in a coin and wait for your snack to pop out?

Behind that simple mechanism lies a carefully crafted digital logic system that detects coins, tracks inserted amounts, and commands the dispenser — all powered by the principles of Finite State Machines (FSMs).

In this article, we’ll walk through the design of a vending machine controller using a Moore FSM model in Verilog HDL, complete with simulation and implementation insights.

What Is a Finite State Machine (FSM)?

A Finite State Machine is a digital design model that transitions between a limited set of states based on inputs and clock events. FSMs are essential in control-based systems such as elevators, password locks, traffic light controllers — and of course, vending machines.

For this project, our vending machine will:

• Accept Nickels (5¢) and Dimes (10¢)
• Dispense an item once 15¢ is collected
• Not return any change

System Overview

The vending machine logic can be divided into three primary modules:

• Coin Detector: Identifies whether a nickel or dime was inserted.
• FSM Controller: Tracks total value and determines when enough money has been inserted.
• Dispenser Control: Activates the mechanism to release the item.

Vending Machine Block Diagram

Inputs and Outputs

The inputs and outputs are:

Inputs:

coin → Encoded signal indicating the type of coin inserted

clk → System clock

reset → Returns the FSM to its start state

Outputs:

open → Signal that triggers the vending mechanism to dispense the product

FSM State Definitions

Our vending machine cycles through four states based on the amount entered:

• S0 → Value = 0¢ → Output = 0 • S5 → Value = 5¢ → Output = 0 • S10 → Value = 10¢ → Output = 0 • S15 → Value = 15¢ → Output = 1 (item released)

State diagram of vending machine

The machine transitions among these states depending on coin inputs. Once the total reaches 15¢, the FSM enters S15, raises the output, and triggers the dispenser.

Moore vs Mealy FSMs

Before coding, it’s important to distinguish between the two major FSM styles:

Moore Machine

• Output depends only on the current state
• Output changes occur synchronously
• More predictable and simpler to design

Mealy Machine

• Output depends on state + inputs
• Responds faster to changes
• Often requires fewer states

Moore Machine State Table Example

For this project, we use a Moore FSM, but the same logic can be reshaped into a Mealy version (a great exercise once you’ve mastered this one).

Verilog Code: Moore FSM for Vending Machine

Below is the Verilog HDL implementation of the FSM:

module moore_vending(
    input clk,
    input reset,
    input [1:0] coin,
    output reg out
    );

    reg [1:0] state, next;

    parameter S0  = 2'b00,
              S5  = 2'b01,
              S10 = 2'b10,
              S15 = 2'b11;

    // State transition on clock/reset
    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= S0;
        else
            state <= next;
    end

    // Output logic (Moore: depends only on state)
    always @(state) begin
        case (state)
            S15: out = 1;
            default: out = 0;
        endcase
    end

    // Next-state logic
    always @(*) begin
        case (state)
            S0:  if      (coin == 2'b01) next = S5;
                 else if (coin == 2'b10) next = S10;
                 else                    next = S0;

            S5:  if      (coin == 2'b01) next = S10;
                 else if (coin == 2'b10) next = S15;
                 else                    next = S5;

            S10: if (coin == 2'b01 || coin == 2'b10)
                            next = S15;
                 else       next = S10;

            S15: if (!reset) next = S15;
                 else        next = S0;
        endcase
    end
endmodule

Testbench for Simulation

The following testbench stimulates the FSM with clock pulses and coin inputs:

module moore_vending_tb;
    reg clk;
    reg reset;
    reg [1:0] coin;
    wire out;

    moore_vending uut (
        .clk(clk),
        .reset(reset),
        .coin(coin),
        .out(out)
    );

    initial begin
        clk = 0;
        forever #5 clk = ~clk;  // Generate clock
    end

    initial begin
        reset = 1;
        coin  = 2'b00;
        #12;
        reset = 0;

        // Insert three nickels
        #2  coin = 2'b01;
        #10 coin = 2'b01;
        #10 coin = 2'b01;
        #10 coin = 2'b00;

        // Reset the machine
        #10 reset = 1;
        #10 reset = 0;

        // Insert two dimes
        #2  coin = 2'b10;
        #10 coin = 2'b10;
        #10 coin = 2'b00;

        #30 $finish;
    end
endmodule

RTL (Register Transfer Level) View

The RTL schematic visually illustrates how the registers, combinational logic, and sequential elements are connected within the design. It allows you to confirm that:

• State transitions have been implemented correctly
• Flip-flops and logic circuits are synthesized as intended

RTL View of Vending Machine

Simulation Results

After running the simulation, you can observe the FSM transitioning through states:

• State progression: S0 → S5 → S10 → S15
• Output (out = 1) goes HIGH only in S15
• Applying reset brings the FSM back to S0.

These results confirm correct functionality of the vending machine FSM.

Simulation results

Conclusion

This project demonstrates how an FSM can be used to design an actual control system like a vending machine. By using a Moore machine, we ensured clean, predictable, and clock-driven behavior.

If you want an extra challenge, try creating the Mealy FSM version — you’ll end up with fewer states and faster output responses, deepening your understanding of state machine design.