How 224G SerDes Enables 1.6T Networking Without Increasing Lane Counts?

As AI clusters continue to expand, GPU computing power is growing at a rate far exceeding network bandwidth, and traditional 112G SerDes is gradually approaching its engineering limits in terms of power consumption, signal integrity, and transmission distance. Meanwhile, the evolution from 800G to 1.6T networking has become an inevitable choice to support the next generation of AI infrastructure. To double the bandwidth without significantly increasing the number of ports and system complexity, the single-channel rate must be increased from 112Gbps to 224Gbps. Therefore, 224G SerDes is not only a key technology for the implementation of 1.6T switches and optical modules, but also an important foundation for driving AI networks towards higher bandwidth, higher density, and higher energy efficiency.

The Evolution of SerDes: From 25G to 224G SerDes

224G SerDes is not an isolated technological upgrade, but rather the result of the continuous evolution of high-speed interconnect technology. For a long time, as network bandwidth demands have continued to grow, SerDes technology has consistently progressed along the path of increasing single-channel speeds to support the continuous expansion of bandwidth in switches, network interface cards (NICs), and optical modules.

Early data center networks primarily used 25G SerDes, achieving 100G interconnects based on NRZ (Non-Return-to-Zero) modulation technology. With the development of cloud computing and large-scale data centers, the industry gradually shifted to PAM4 (4-Level Pulse Amplitude Modulation) modulation technology, increasing single-channel speeds to 50G and 112G, laying the foundation for the widespread adoption of 400G and 800G networks.

However, with the continuous expansion of AI clusters, 112G SerDes has gradually approached its engineering limits in terms of signal integrity, power consumption, and bandwidth expansion. To meet the demands of next-generation 1.6T networking for higher bandwidth density and lower cost per bit, the industry has begun evolving towards 224G SerDes.

Like 112G, 224G SerDes still employs PAM4 modulation technology, but its signal rate is doubled, placing higher demands on chip design, packaging processes, PCB materials, connector performance, and heat dissipation capabilities. Therefore, the significance of 224G lies not only in increased bandwidth but also in driving the development of switches, optical modules, and the entire network architecture towards higher density and higher energy efficiency, laying the foundation for the arrival of the 1.6T networking era.

What is 224G SerDes?

SerDes (Serializer/Deserializer) is a core interface technology in high-speed network devices. It converts parallel data output from an ASIC (Instrumentation Science Processing Unit) into high-speed serial signals for transmission and restores the data to parallel at the receiving end. By reducing the number of physical I/O connections, SerDes achieves higher data transmission bandwidth within a limited package space, making it a crucial foundation for modern data centers, AI clusters, and high-performance computing networks.

224G SerDes is a next-generation high-speed SerDes technology with a single-channel transmission rate of 224Gbps, doubling the bandwidth of the previous generation 112G SerDes. As AI training clusters continue to expand, networks are placing higher demands on bandwidth density, power efficiency, and port expansion capabilities. 224G SerDes is gradually becoming a core technology foundation for 800G and 1.6T transceivers, switches, and the OSFP224 ecosystem.

Why Does a 1.6T Networking Require 224G SerDes?

1.6T networking require 224G SerDes because only by increasing single-channel bandwidth can 1.6T-level interconnects be achieved with acceptable power consumption, package size, and system complexity.

Fewer Channels: Compared to 112G SerDes, the most significant advantage of 224G SerDes is its ability to reduce the number of channels required for the same bandwidth. For example, a traditional 800G optical transceiver typically requires eight 112G electrical channels, while with 224G SerDes, only four channels are needed to achieve the same transmission capacity. This not only simplifies the module’s internal architecture and host PCB design but also helps reduce power consumption and improve system reliability.

Supporting the Evolution of 1.6T Optical Interconnects: 224G SerDes paves the way for the 1.6T networking era. If 112G SerDes were used to build 1.6T optical modules, 16 electrical channels would be required, which would not only be limited by package size but also bring greater power consumption and heat dissipation challenges. Based on 224G SerDes, only 8 channels are needed to achieve 1.6T transmission capacity, making next-generation pluggable optical modules such as OSFP224 a reality.

Improved Port Density and Energy Efficiency: By increasing the single-channel rate and reducing the number of channels, 224G SerDes not only increases the port density of switches and optical modules but also further optimizes system energy efficiency. Therefore, it is considered a key underlying technology supporting next-generation AI data center networks and 1.6T interconnect architectures.

What’s the Difference Between 224G SerDes and 112G SerDes?

For 400G and 800G networks, 112G SerDes are sufficient to meet bandwidth requirements. However, as networks evolve towards 1.6T, 112G SerDes begin to face challenges in terms of bandwidth density, package space, and power consumption.

The biggest difference lies in the number of channels required to achieve 1.6T bandwidth. Building a 1.6T transceiver based on 112G SerDes typically requires 16 electrical channels, which not only increases PCB routing complexity but also occupies more package space and brings greater power consumption and heat dissipation pressure. For standard pluggable modules, this design is approaching the physical and thermal design limits.

In contrast, 224G SerDes increases single-channel bandwidth to 224Gbps, requiring only 8 channels to achieve 1.6T transmission capability. With the number of channels reduced by half, the internal architecture of the module is simpler, the high-speed signal path is shorter, and the system design complexity is reduced accordingly.

Therefore, for the next-generation 1.6T networking, 224G SerDes is not only a speed upgrade, but also a key technology for achieving high-density, deployable, and scalable 1.6T optical interconnects. Without 224G SerDes, although a 1.6T networking can theoretically be achieved, its cost, power consumption, and packaging complexity will increase significantly, making it difficult to meet the deployment requirements of large-scale AI clusters.

Challenges Related to 224G SerDes

While 224G SerDes provides crucial support for 1.6T networking, doubling the single-channel speed also presents higher technical challenges. From chips to optical modules and switch system design, the entire industry chain needs to address challenges related to signal strength, power consumption, and heat dissipation.

• Signal Integrity Challenges

With transmission rates increasing to 224Gbps, signal loss in PCBs, connectors, and copper interconnects increases significantly. To ensure signal quality, systems typically require ultra-low loss (ULL) materials, optimized high-speed cabling designs, and minimized signal transmission paths.

• Increased DSP and FEC Complexity

Higher signal rates mean increased difficulty in bit error rate control. To ensure link stability, 224G systems rely on more advanced digital signal processing (DSP) technologies and enhanced forward error correction (FEC) algorithms for real-time signal compensation and error correction, thereby ensuring data transmission reliability. According to TSMC’s technical data, compared to the 5nm process, the 3nm process can achieve approximately 10–15% performance improvement and 25–30% power consumption reduction. For more information, please refer to: Why Choose 3nm DSP Chip for 1.6T Transceivers?

• Increased Power Consumption and Heat Dissipation Pressure

The high-speed operation of 224G SerDes generates higher power consumption and heat, placing greater demands on the heat dissipation capabilities of modules and systems. Therefore, next-generation OSFP224 optical modules typically require optimized heat dissipation structures, airflow designs, and packaging solutions to ensure stable operation in high-density deployment environments.

Overall, 224G SerDes represents not only a bandwidth upgrade but also drives simultaneous advancements in materials, chips, packaging, and heat dissipation technologies. Solving these challenges will directly impact the large-scale deployment of 1.6T networking.

Conclusion

As AI training and inference clusters continue to scale up, network bandwidth is becoming a key factor affecting the efficiency of computing power release. The evolution from 112G to 224G SerDes not only doubles the single-channel speed but also solves the core challenges of 1.6T networking in terms of channel count, port density, power consumption, and packaging design. Therefore, 224G SerDes has become a crucial technological pillar for building next-generation 1.6T AI network infrastructure.

As a solutions provider for AI data centers and high-performance computing networks, NADDOD possesses extensive experience in 1.6T networking deployment and offers a complete product portfolio including 1.6T transceivers and 1.6T cables. Furthermore, with ample inventory and a stable supply chain, NADDOD can ensure rapid delivery and continuous expansion of large-scale AI cluster projects, helping customers accelerate the construction of next-generation AI infrastructure.