Between glossy AI headlines and real datacenters lies a very physical supply chain.

The Bottleneck Nobody Is Pricing In: Where AI Compute Really Breaks

Every layer that looks solved hides another constraint beneath it.

I’ve been following this question through several turns of the semiconductor cycle: not whether AI demand is real, but whether the physical stack beneath it can scale on the same timeline.

§1 The Illusion of Infinite Compute

The headlines say NVIDIA is winning. The hyperscalers are spending. The models are getting bigger.

But the real question is not where demand is going. It is whether compute can still be built, physically, fast enough to meet it.

Answering that seriously means tracing the full physical stack — from silicon wafers to memory stacks, from packaging interposers to substrate materials — and asking at each layer: can this actually scale at the speed the demand curve now assumes?

The uncomfortable answer is the same at every layer: not yet, and not linearly.

TSMC’s management has been hinting at this. In its 1Q25 earnings call, the company said it was working hard to double CoWoS capacity in 2025 to narrow a persistent supply‑demand gap, not to declare victory over it. Demand is still running ahead of the ecosystem that has to physically deliver it.

This piece maps three layers of that gap. Each is real. Each has a different resolution timeline. And at least one of them is still largely absent from mainstream investor conversation.

§2 CoWoS: The Integration Layer That Cannot Be Rushed

Most AI infrastructure coverage treats packaging as a backend afterthought — something that happens after the “real” engineering is done. That framing is wrong, and it causes analysts to miss where the real constraint sits.

CoWoS — Chip on Wafer on Substrate — is not just a packaging step. In TSMC’s own technical language, it is an integration platform for AI and ultra‑high‑performance computing. It physically bonds logic chiplets and HBM stacks on a large‑area silicon interposer, at densities and interconnect speeds that no other production‑scale approach currently matches.

That is why you cannot simply “open another line.” A conventional OSAT packaging line and a CoWoS line share very little in equipment, process know‑how, or yield‑learning. The interposer itself must be built at leading‑edge fab precision. High‑volume bonding of multiple HBM stacks to logic dies, with acceptable yield, took years to develop and cannot be cloned on demand.

TSMC’s own posture makes this clear. Management has guided to roughly doubling CoWoS capacity in 2025, an aggressive ramp that also implicitly admits how tight the starting point was. Additional advanced‑packaging capacity in Arizona is coming — but the key word is additional, not sufficient. Through 2025 and into 2026, the company has consistently talked about “narrowing” the gap rather than clearing it.

CoWoS is the integration layer that turns AI silicon into a shippable system, not a minor backend step.

For investors: CoWoS capacity is the near‑term gating factor on how many H100/B200‑class systems actually ship in any given quarter. NVIDIA’s revenue recognition and hyperscaler utilisation rates are downstream of this constraint.

Figure1. Even with aggressive CoWoS expansion, modelled capacity still lags projected AI demand through most of the decade.

§3 HBM: Not Just a Memory Story, but a Capacity‑Allocation Story

High Bandwidth Memory is usually where supply‑chain analysis stops once it goes deeper than CoWoS. Yet even at that level, the standard narrative — “SK hynix leads, Samsung is catching up, Micron is entering” — understates how rigid the structure really is.

By late 2025, Counterpoint and other trackers still showed SK hynix with roughly the mid‑50s percent of the HBM market, with Samsung in the low‑20s and Micron a smaller but growing third player. This is not a wide‑open market. It is a functional duopoly with a clear leader, and that leader remains NVIDIA’s primary HBM supplier.

This does not change quickly, and not for lack of ambition or capital. It changes slowly because of physics and the process.

HBM3E stacks multiple DRAM dies with through‑silicon vias at tolerances where yield management is genuinely hard. Qualification with customers like NVIDIA is not a formality. It is a multi‑quarter gauntlet of thermal validation, signal‑integrity testing, and system‑level burn‑in. A trailing supplier does not catch up just by breaking ground on a new fab; it catches up by surviving that qualification cycle, while market demand keeps compounding.

Layer on top of that the wafer constraint. SK Group’s leadership and industry reports have repeatedly emphasized that HBM is extremely wafer‑intensive, warning of significant wafer undersupply and noting that new wafer capacity takes four to five years to bring online. Now put that against an AI demand curve that seems to re‑accelerate every six months.

HBM is not only a memory story; it is a capacity‑allocation story across wafers, yields, validation, and customer trust.

Samsung’s response — pushing longer‑term supply agreements to lock in AI memory customers — is itself a signal. This is no longer a spot‑market commodity dynamic; it is a platform‑supply competition, and positions established over the next few years are likely to persist.

Figure2.HBM remains a functional duopoly today; qualification cycles and wafer intensity make share shifts slow, not sudden.

§4 Substrate and Materials: The Constraint Almost Nobody Models

This is also the layer I see written about the least — and potentially the one that lingers the longest.

Every CoWoS package, every advanced AI accelerator, sits on an ABF substrate — a laminate built using Ajinomoto Build‑up Film as the core dielectric. Ajinomoto’s own materials and industry reports say ABF holds more than 95% share of the global market for insulating films used in high‑performance semiconductors and in CPU/GPU substrates. That is not a rounding error. It is the market structure.

Ajinomoto’s technical and IR documents list servers and high‑performance computing as primary ABF application areas. The material is not a generic film; it needs controlled‑environment manufacturing, multi‑layer lamination at tight specs, and constant process development as packages grow more complex.

And those packages are getting more complex. Substrate makers such as Nan Ya PCB have roadmaps for 2025–2026 that point to higher layer counts, larger body sizes, and finer line‑and‑space geometries for AI and HPC applications. The AI era is not just consuming more substrate area; it is consuming substrate at specifications that are harder to make and that fewer fabs can reliably produce.

Ajinomoto plans to invest at least ¥25 billion by 2030 to expand ABF capacity by roughly 50%. That number is reassuring — they are leaning in — but the 2030 horizon is also telling. It implicitly acknowledges that this is not a constraint that goes away in a couple of years.

Markets often overestimate flexibility at the chip‑design layer and underestimate rigidity at the materials‑and‑substrate layer. For anyone tracking dependency concentration, ABF may be the single most concentrated chokepoint in the entire AI infrastructure stack — and it still receives a fraction of the analytical attention lavished on TSMC or SK hynix.

Figure3. ABF capacity is stepping up, but the staircase still trails the curve of AI demand growth.

§5 Resolution Timelines: Who Clears First, Who Doesn’t

For investors and operators, the key question is not whether these bottlenecks exist — they do — but when each one eases, and in what sequence.

CoWoS: earliest to ease, but not soon. TSMC is still expanding aggressively; Arizona capacity is on the way; advanced packaging has become a capex line item in its own right. The gap is narrowing, but “narrowing” through 2026 still means constrained. CoWoS is the bottleneck most likely to show visible relief in the 2026–2027 window, but it is unlikely to simply disappear ahead of that.

HBM: structurally tight for longer. Combine SK’s comments on wafer‑intensity and multi‑year wafer lead times with a demand curve that keeps steepening, and it becomes hard to build an optimistic “quickly balanced” HBM scenario. Samsung’s push toward long‑term agreements signals that even suppliers expect tightness to persist for years, not quarters. SK Hynix will likely remain dominant; Micron’s entry adds optionality more than near‑term volume.

Substrate and materials: the most underappreciated drag. Ajinomoto’s 2030 investment horizon, together with ABF spec escalation at substrate makers like Nan Ya, describes a constraint that is intensifying in technical difficulty even as nameplate capacity grows. This is not a bottleneck that clears the moment a new building opens; it clears when the full chain — materials, qualification, manufacturing at the next complexity node — matures.

Put differently: CoWoS may ease first. HBM may stay structurally tight through much of the decade. Substrate and material constraints may quietly become the main reason timelines slip.

For investors, the headline winner here is obvious. The less obvious beneficiaries sit in the least‑discussed layers: advanced‑packaging equipment vendors, specialty substrate manufacturers, and any company that can credibly ship an ABF alternative or a competing interposer material.

For operators, three metrics are worth watching: CoWoS lead times (a proxy for near‑term AI system supply), HBM allocation terms and contract length (a proxy for mid‑term platform lock‑in), and ABF capacity/expansion announcements out of Ajinomoto and its substrate partners (a proxy for the constraint most financial models still treat as background noise).

The compute is real. The demand is real. But between the architecture diagram and the data‑center floor is a physical world with its own clock speed — and right now, that clock is still running slower than the one being priced into the market.

Figure4. The real AI bottlenecks are still found in notebooks and process diagrams, not just GPU launch slides.

Author

Sinclair Huang is a researcher and advisor focused on semiconductors, AI infrastructure, and biotech. He writes about how physical supply chains shape the trajectory of compute and capital markets.

Further reading

• TSMC Q1 2025 earnings call transcripts and commentary on CoWoS capacity.
• Counterpoint and other HBM market‑share analyses through 2025.
• Ajinomoto IR and industry reports on ABF share and 2030 capacity investments.
• Coverage of SK hynix and Samsung HBM roadmaps and qualification progress.

Disclaimer

This article is for informational and educational purposes only and does not constitute investment advice or a recommendation to buy or sell any security. All views expressed are the author’s personal opinions, based on publicly available information believed to be reliable but not guaranteed as to accuracy or completeness. Readers should do their own research and consult qualified professionals before making investment decisions.

Hashtags

AIInfrastructure #Semiconductors #TSMC #HBM #NVIDIA #AdvancedPackaging #CoWoS #ABF #SupplyChain #Investing

Author’s note This essay reflects my current structural reading of the AI compute supply chain as of March 2026. It is not meant as a short-term market call, but as a longer-horizon view on where physical bottlenecks may persist even as capital and narratives move faster than industrial reality. Near-term conditions can still change with geopolitics, energy, logistics, and new capex decisions.