Low Power RTL design

Low power RTL (Register Transfer Level) design is an important aspect of digital system design that is aimed at minimizing the dynamic and static power consumption of the circuit while maintaining its functionality and performance. Low power designs are crucial in various applications such as portable handheld devices powered by batteries. In plug-in devices, power efficiency is very crucial as it affects the overall cost of building & maintaining the system. In AI chips especially the ones used in data centers and High Performance Computing (HPC).

Here are some common techniques used in low-power RTL design. The intricate RTL design incorporates one or more of these design techniques to minimize power consumption.

1. Clock gating

This is a widely used technique to reduce power consumption in digital circuits. The principle is to turn-off clocks to parts of the circuit which are inactive or logic that are unused during certain phases of operation thus reducing unnecessary switching activity which in-turn reduces dynamic power consumption. Reducing switching activity also reduces the heat dissipated by the circuit and extends battery life.

The overhead of adding additional logic gates and control signals increases the complexity of the designs, increasing the design & verification efforts. In certain parts of the circuit like registers or flip-flops care must be taken to add Retention flops to retain the previous state before turning-off the clocks, hence increasing the design size. Adding clock gating to certain parts of the design can lead to synchronization issues resulting in Clock-domain Crossing (CDC) errors especially in multi-clock domain systems.

2. Power gating

This technique is efficient in reducing power consumption in Integrated Circuit (IC’s) , System on Chip (SoC’s) and processors. When the system operates in low power mode, the blocks or modules which are inactive are turned-off. This is achieved by using power switches such as MOSFETs which are placed in between power supply and circuit blocks. When the block is in idle state the switch cuts off the power supply to the block. This technique reduces both static power consumption (leakage current) and dynamic power consumption (caused due to switching activity) hence it is widely used in battery powered devices, embedded systems, multi-core processors and energy efficient computing systems where power consumption is very critical.

The overhead of this technique is to manage the wake-up latency i.e. the time taken to power-on/off the block. This requires an additional circuit in the design to manage the switching between idle state and active state without degrading the performance.

3. Dynamic Voltage Scaling

Dynamic Voltage Scaling (DVS) is a technique used to regulate the power consumption in a digital circuit by varying the voltage and frequency in real time based on the workload requirement. The equation, P ​= C⋅V²⋅f states that P(dynamic power) is proportional to V(voltage) and f(clock frequency). By lowering the supply voltage and clock frequency the system consumes less power but also reduces the system performance operating at low speed. When the workload is high the system operates at high voltage & frequency and gradually scales down dynamically when the workload lowers. This technique is combined with other low-power techniques and mainly applied in servers and High Power Computing(HPC) where energy consumption is a major concern.

This technique requires additional hardware components like voltage regulators and frequency scaling mechanisms which increases the complexity of the design. During scaling care must be taken to maintain the stability of the circuit not to allow the voltage to fall below the threshold value as it might disrupt the functionality of the entire circuit.

4. Dynamic Frequency Scaling(DFS)

This technique is similar to DVS, but here only the clock frequency of the circuit is varied by keeping the supply voltage constant. It is also based on the same principle as DVS, where P(dynamic power) is proportional to f(clock frequency). It is less aggressive in terms of power reduction compared to DVS, hence applied in battery operated devices like mobile phones & laptops, and embedded systems like IoT’s. DFS helps optimize energy usage without sacrificing too much performance, especially when the device is not performing computationally intensive tasks.

5. Multiple VDD domain

The chip design is divided into different segments and the power supply is varied based on the performance requirement of each segment. For Eg, high performance processor cores will require higher VDD compared to low performance peripherals like sensors or control units. The design has separate voltage rails for each VDD domain and a power delivery network (PDN) ensures each part of the chip gets the required voltage without unnecessary overhead. In multiple VDD domain design, isolation cells are used to prevent unwanted current between different domains and level shifters are used to connect segments operating in different voltage domains.

6. Multiple VT domain

Threshold voltage(VT) refers to minimum voltage required by the transistors to turn on and allow current flow. Lower VT allows faster switching of transistors but leads to high leakage current and Higher VT reduces the leakage current but reduces performance due to slower switching speeds. Hence based on the functionality, the chip can support different VT levels. For Eg, processors or high speed data path can have lower VT and low speed peripherals and memory units can have high VT.