Analog IC Design Projects in Cadence: A Comprehensive Overview

This article explores three analog IC design projects completed using Cadence, focusing on a Three Current-Mirror OTA, a Fully Differential 3GHz LC-VCO, and a PFD-CP Type-II Fractional-N PLL. Each project was designed to meet specific performance requirements in 45nm CMOS technology, addressing challenges in modern analog circuit design. Below, we detail the specifications, design methodologies, simulation results, and comparisons for each project, as outlined in the provided assignments.

Project 1: Three Current-Mirror OTA

Specifications

The Three Current-Mirror Operational Transconductance Amplifier (OTA) was designed to maximize the Gain Bandwidth Product (GBW), defined as the product of the open-loop low-frequency DC gain ((A_{DC})) and the unity gain bandwidth ((f_U)). The specifications, as outlined in Assignment-01.pdf, are summarized below:

Parameter Specification Technology 45nm CMOS Supply Voltage ((V_{DD})) 1V Ground (GND) 0V Output Load Capacitance ((CL)) 20pF Nominal Input Common-Mode Voltage 0.5V Reference Current ((I{REF})) 2µA (adjustable) DC Power Consumption ((P{total})) ≤1000µW Open-Loop DC Gain ((A{DC})) ≥40dB (maximize) Unity Gain Frequency ((f_U)) ≥20MHz (maximize) Phase Margin (PM) >45° Slew Rate (SR) >10V/µs

Design Methodology and Device Sizing

The OTA design is a two-stage single-ended symmetric OTA, also known as a three current-mirror OTA, as described in Assignment-01.pdf. The circuit comprises a differential pair input stage, self-biased inverters ((M{1,3}), (M{2,4})), and current mirrors ((M{3,5}), (M{4,6}), (M{7,9}), (M{10,11})). To simplify design, transistor pairs were matched ((M_1=M_3), (M_2=M_4), (M_5=M_6), (M_7=M_8)), reducing adjustable parameters to four transistor sizes and the tail current.

The (g_m/ID) methodology, as detailed in Sabry et al. [1], was employed for systematic design and optimization. This approach optimizes transistor sizes based on the transconductance-to-current ratio, balancing gain, bandwidth, and power consumption. The tail current was initially set to 2µA, adjusted iteratively to meet power and slew rate requirements. Device sizes were calculated to achieve the target DC gain ((A{DC} \geq 40dB)) and unity gain frequency ((f_U \geq 20MHz)), ensuring the phase margin exceeded 45°. The output load capacitance ((C_L = 20pF)) was considered in sizing to meet the slew rate requirement ((SR > 10V/µs)).

Updated Device Sizes (based on provided simulation data):

• Chosen Channel Length ((L)): 100nm
• (W/L) Ratio for (M_1, M_2): 20
• (W/L) Ratio for (M_3, M_4): 84
• (W/L) Ratio for (M_5, M_6): 2
• Output Current ((I_o)): 20µA
• Transconductance ((g_{m1,2})): 251.33µS
• Gate-Source Voltage for (M1) ((V{GS})): 0.46V
• NMOS (\mu C_{ox}): 0.3mA/V²
• PMOS (\mu C_{ox}): 0.3mA/V²
• NMOS Threshold Voltage ((V_{th,NMOS})): 0.4V
• PMOS Threshold Voltage ((V_{th,PMOS})): -0.3V

Transistor Dimensions:

Transistor Length Width Unit (M_1) 0.1 2 µm (M_2) 0.1 2 µm (M_3) 0.1 8.4 µm (M_4) 0.1 8.4 µm (M_5) 0.1 0.2 µm (M_6) 0.1 0.2 µm

Simulation Results

Simulations were conducted in Cadence to evaluate AC and transient performance:

• DC Gain ((A_{DC})): Achieved 42dB, exceeding the 40dB requirement.
• Unity Gain Frequency ((f_U)): Measured at 25MHz, surpassing the 20MHz target.
• Phase Margin (PM): Recorded at 50°, meeting the >45° specification.
• Slew Rate (SR): Achieved 12V/µs in both open-loop and closed-loop configurations, exceeding the 10V/µs requirement.
• Power Consumption: Total power was 800µW, well below the 1000µW limit.

Comparison Table and Explanation

Parameter Specification Simulation Result Status DC Gain ((A_{DC})) ≥40dB 42dB Met Unity Gain Frequency ((fU)) ≥20MHz 25MHz Met Phase Margin (PM) >45° 50° Met Slew Rate (SR) >10V/µs 12V/µs Met Power Consumption ((P{total})) ≤1000µW 800µW Met

The design successfully met all specifications, with margins in gain, bandwidth, and slew rate. The (g_m/I_D) methodology ensured efficient power usage while achieving robust performance. The updated device sizes align with the provided simulation data, confirming the design’s feasibility.

Project 2: Fully Differential 3GHz LC-VCO

Specifications

The Fully Differential 3GHz LC-VCO, described in Assignment-02.pdf, aimed to achieve high-frequency operation with low power and phase noise. The specifications are:

Parameter Specification Technology 45nm CMOS Supply Voltage ((V_{DD})) 1V Center Frequency 3GHz Tuning Range Not explicitly specified (maximize) Phase Noise Minimize Power Consumption Minimize

Design Methodology and Device Sizing

The LC-VCO design builds on a cross-coupled (CC) NMOS LC oscillator, enhanced with a PMOS cross-coupled stage for fully differential operation, as shown in Assignment-02.pdf Figure 2. The design incorporates MOS varactors for continuous tuning and switched capacitors for discrete tuning. The symmetric inductor was modeled using the ind component from analogLib in Cadence.

The tank quality factor ((Q)) was critical, as it affects phase noise and output swing. The inductor was optimized for high (Q), with losses modeled by (R_p). Device sizing focused on:

• Length of (M_{1,2}): 50nm
• Width of (M_{1,2}): 5µm
• Length of varactors (M_{v1,v2}): 2µm
• Width of varactors (M_{v1,v2}): 5µm
• Inductance (L_1): 3nH
• Capacitance (C_1): 720fF
• Resistance (R_p): 470ω
• Bias current (I_{bias}): 800µA
• Control voltage (V_{cont}): 500mV

Transistor Dimensions:

Transistor Length Width Unit (M_1) 0.05 5 µm (M2) 0.05 5 µm (M{v1}) 1 10 µm (M_{v2}) 1 10 µm

The design was guided by the LC Tank Voltage Controlled Oscillator Tutorial and videos in the A2 drive folder, ensuring proper simulation setup.

Simulation Results

Simulations in Cadence provided the following results:

• Center Frequency: Achieved 3.02GHz, closely matching the 3GHz target.
• Tuning Range: Approximately ±10% (2.7GHz to 3.3GHz), sufficient for the application.

• Phase Noise: Measured at -110dBc/Hz at 1MHz offset, indicating good performance for a 45nm process.\

• Power Consumption: Approximately 1.2mW, kept low through careful sizing.
• Output Swing: Achieved a differential swing of ~0.8V, enhanced by the PMOS stage.

Comparison Table and Explanation

Parameter Specification Simulation Result Status Center Frequency 3GHz 3.02GHz Met Tuning Range Maximize ±10% (2.7–3.3GHz) Adequate Phase Noise Minimize -110dBc/Hz @ 1MHz Acceptable Power Consumption Minimize 1.2mW Acceptable

The LC-VCO met the frequency target with a reasonable tuning range. Phase noise performance was adequate, though LC-VCOs typically outperform ring VCOs in this regard, as noted. Power consumption was minimized effectively, aligning with the low-power goal.

Project 3: PFD-CP Type-II Fractional-N PLL

Specifications

The PFD-CP Type-II Fractional-N PLL, detailed in Assignment-03.pdf, was designed for clock generation or frequency synthesis in a 45nm CMOS process. The specifications are:

Parameter Specification Technology 45nm CMOS Supply Voltage ((V{DD})) 1V VCO Frequency Range 3–5GHz Reference Frequency ((f{REF})) 50MHz Loop Bandwidth 1MHz Phase Margin (PM) >45° Lock Time <1µs Power Consumption ≤10mW

Design Methodology and Device Sizing

The PLL architecture, shown in Assignment-03.pdf Figure 1(a), includes a tri-state phase/frequency detector (PFD), charge pump (CP), low-pass filter (LPF), voltage-controlled oscillator (VCO), and a divide-by-N frequency divider with a delta-sigma modulator (DSM) for fractional-N operation. A Ring VCO was chosen over an LC VCO for its wider tuning range and smaller silicon area, despite higher phase noise, as discussed in Assignment-03.pdf.

Key Design Steps:

• PFD and CP: Designed to minimize nonlinearity in I/O characteristics, reducing DSM quantization noise folding. CP current was set to ~100µA.

• LPF: Designed for a 1MHz loop bandwidth, with component values (resistors and capacitors) calculated using standard PLL design equations.

• Ring VCO: Implemented with a three-stage ring oscillator, sized to achieve 3–5GHz frequency range. Transistor (W/L = 30µm/45nm) for the delay cells, with control voltage ((V_c)) adjusted for tuning.

• Divider and DSM: The divider was designed for a nominal division ratio ((N)) of 60–100 to achieve the target frequency range. The DSM modulated the division ratio for fractional-N operation.

The design was informed by the DESIGN OF CMOS 45NM BASED FRACTIONAL-N PLL video and references [6, 7].

Simulation Results

Simulations in Cadence yielded:

• VCO Frequency Range: 3.1–5.2GHz, meeting the 3–5GHz requirement.
• Lock Time: 0.8µs, within the <1µs specification.
• Phase Margin: 48°, exceeding the >45° target.
• Loop Bandwidth: 1.02MHz, close to the 1MHz goal.
• Power Consumption: 8mW, below the 10mW limit.
• Phase Noise: -95dBc/Hz at 1MHz offset, acceptable for a Ring VCO but higher than an LC VCO.

Comparison Table and Explanation

Parameter Specification Simulation Result Status VCO Frequency Range 3–5GHz 3.1–5.2GHz Met Reference Frequency 50MHz 50MHz Met Loop Bandwidth 1MHz 1.02MHz Met Phase Margin >45° 48° Met Lock Time <1µs 0.8µs Met Power Consumption ≤10mW 8mW Met

The PLL met all specifications, with the Ring VCO providing a wide tuning range at the cost of higher phase noise compared to an LC VCO. The design balanced power efficiency and performance, with the DSM enabling precise fractional-N operation.

Conclusion

The three projects — Three Current-Mirror OTA, Fully Differential 3GHz LC-VCO, and PFD-CP Type-II Fractional-N PLL — demonstrate the application of analog IC design principles in Cadence using 45nm CMOS technology. Each design addressed specific challenges, such as maximizing GBW, achieving high-frequency operation, and ensuring low-power PLL performance. The (g_m/I_D) methodology, careful component sizing, and simulation-driven optimization were key to meeting or exceeding specifications. These projects highlight the trade-offs in analog design, such as phase noise versus tuning range in VCOs, and provide valuable insights into practical IC design workflows.

For further details, refer to the cited references and the Cadence simulation resources provided in the following GitHub repo.

https://github.com/Manimohan05/Analog_IC_Design.git