The Physics Behind Logic Gate Delay

What Really Determines Logic Gate Speed? From Electrons to CMOS

Modern CPUs are built using CMOS (Complementary Metal–Oxide–Semiconductor) technology. A CMOS CPU contains billions of transistors integrated on a silicon chip. These transistors form logic gates, which perform basic Boolean operations used in digital computation.

CMOS uses two complementary transistor types: NMOS and PMOS. This structure allows circuits to achieve high speed with very low static power consumption, since current mainly flows during switching.

The performance of a CMOS CPU depends on the switching speed of its transistors, which is influenced by carrier mobility and channel resistance. When a gate input changes, the output responds after a propagation delay, determined by transistor properties as well as load capacitance, fan-out, and interconnect length. These factors collectively set the maximum operating speed of the CPU.

Since CPU operations involve signals passing through many gates in sequence, the total delay of these gates limits the maximum clock frequency of the processor. Faster gates allow signals to propagate more quickly through the circuit, enabling the CPU to operate at higher speeds.

The delay of a CMOS gate is mainly determined by the resistance of the conducting transistors and the capacitance at the output node. A common approximation is:

where:

The clock frequency of a CPU is therefore limited by the critical path delay:

This means that faster gates (smaller R or C) allow higher CPU clock frequencies, while slower gates increase the total delay of the circuit.

If we assume that the propagation delay difference between NAND and NOR gates is about 5–15 ps, this delay accumulates when gates are connected in sequence along a logic path.

Simple example

Assume a logic path contains 10 gates.

If each NOR gate is 10 ps slower than a NAND gate:

This means the signal arrives 100 ps later compared to a path built with faster gates.

Slightly larger small circuit

If a small logic block contains 30 gates:

Because modern CPUs contain millions of gates, even picosecond-level differences accumulate along long logic paths. For this reason, digital designers often prefer NAND-based logic structures, since they tend to be faster in CMOS implementations.

How Electron Movement Affects Delay

At the lowest level, the switching speed of a CMOS logic gate is determined by the movement of charge carriers inside the transistor channel. When a gate input changes, an electric field forms across the transistor, causing carriers (electrons in NMOS or holes in PMOS) to move through the semiconductor.

This motion is described by the drift velocity of the carriers:

Higher mobility allows carriers to move faster, which increases the current flowing through the transistor.

The current in a MOSFET can be approximated as:

Since the gate delay depends on how fast the output capacitance can be charged or discharged:

higher carrier mobility → larger current → faster charging/discharging → smaller delay

In silicon, electron mobility is about 2–3× higher than hole mobility, which is why NMOS transistors switch faster than PMOS. This physical difference is one of the reasons why some CMOS logic structures (like NAND) tend to be faster than others.

Ultimately, the speed of a CMOS CPU is a delicate dance between physics and engineering: electrons racing through NMOS and PMOS channels, transistors charging and discharging capacitive loads, gates switching under fan-out constraints, and signals traveling along interconnects. Together, these microscopic factors add up to determine how fast your processor can truly “think”.