VHDL Part 1 — Setting Up a VHDL Development Environment with VS Code and the Command Line

Introduction

If you’re serious about digital design — especially working toward building a CPU — you need a workflow that is:

• Deterministic (no hidden GUI magic)
• Scriptable (CI/CD compatible)
• Simulator-driven (test-first hardware design)

This guide walks through setting up a modern VHDL workflow using:

• Visual Studio Code
• GHDL
• GTKWave for waveform analysis

Step 1 — Install VS Code

Download and install:

• Visual Studio Code

Recommended Extensions

Install from Extensions (Ctrl + Shift + X):

• VHDL Language Support
• Error Lens (optional but useful)

Step 2 — Install GHDL (VHDL Simulator)

Linux (Debian/Ubuntu)

sudo apt update
sudo apt install ghdl

macOS

brew install ghdl

Windows

Use:

• MSYS2 + pacman
• Or prebuilt binaries

Step 3 — Install GTKWave

sudo apt install gtkwave

Step 4 — Verify Installation

ghdl --version

You should see version info for GHDL.

Step 5 — Create a Project

mkdir vhdl-project
cd vhdl-project
mkdir src tb build
code .

Step 6 — Terminal Workflow (Critical)

Open Terminal in VS Code

Open terminal — Ctrl + `` New terminal —Ctrl + Shift + ` Split terminal —Ctrl + Shift + 5`

Step 7 — First VHDL File

Create src/clock.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity clock is
    Port ( clk : in STD_LOGIC;
           led : out STD_LOGIC );
end clock;
architecture Behavioral of clock is
begin
process(clk)
begin
    if rising_edge(clk) then
        led <= not led;
    end if;
end process;
end Behavioral;

Step 8 — Testbench

Create tb/clock_tb.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity clock_tb is
end clock_tb;
architecture test of clock_tb is
signal clk : STD_LOGIC := '0';
signal led : STD_LOGIC;
begin
uut: entity work.clock
    port map(clk => clk, led => led);
process
begin
    while true loop
        clk <= '0'; wait for 10 ns;
        clk <= '1'; wait for 10 ns;
    end loop;
end process;
end test;

Step 9 — Compile and Run

ghdl -a src/clock.vhd
ghdl -a tb/clock_tb.vhd
ghdl -e clock_tb
ghdl -r clock_tb --vcd=wave.vcd

Step 10 — View Waveform

gtkwave wave.vcd

You should see:

• Clock toggling
• LED flipping each cycle

Key Takeaways

You now have a full HDL workflow:

1. Write module
2. Write testbench
3. Simulate
4. Inspect waveform

This is exactly how professional digital design works.