FPGA on Red Pitaya Series [5/5]: Automating Vivado with TCL Scripts
We have reached part 5 of our hybrid architecture tutorial involving C, Vivado, FPGAs, and Zynq processors running on the Red Pitaya. The…
FPGA on Red Pitaya Series [5/5]: Automating Vivado with TCL Scripts
We have reached part 5 of our hybrid architecture tutorial involving C, Vivado, FPGAs, and Zynq processors running on the Red Pitaya. The hardware has been designed and sorted out. Everything looks beautiful. The final click before glory? Press Generate Bitstream and watch the real physical .bin file appear, ready for your Linux software to devour and send straight into the transistor chips. Right? Very wrong.
The board will go silent inside a nightmare bug called endianness. Let me show you how I solved this annoying issue automatically with Tcl, without typing Linux commands every time.
Step 1: Create the TCL Script
First, we need to put the command in a separate text file.
- Open a text editor (Notepad or Vivado’s own editor).
- Paste the following content (make sure the
.bitfile name matches yours):
# Script to convert Big Endian BIN (Vivado) to Little Endian (Zynq Linux)
# 1. Define the input file name (The .bin generated by Vivado)
# Usually it is your top module name + .bin
set input_file "design_1_wrapper.bin"
# 2. Define the output file name (What goes to the Red Pitaya)
set output_file "leds_linux.bin"
puts "--> Starting Endianness conversion: $input_file -> $output_file"
if {[file exists $input_file]} {
# Opens input file in Binary mode
set in [open $input_file rb]
fconfigure $in -translation binary
set data [read $in]
close $in
# THE MAGIC:
# "I*" = Reads everything as Unsigned Big Endian Integers (Input file default)
# "i*" = Writes everything as Little Endian Integers (Zynq default)
binary scan $data I* integers
set output_data [binary format i* $integers]
# Saves the converted file
set out [open $output_file wb]
fconfigure $out -translation binary
puts -nonewline $out $output_data
close $out
puts "--> Success! File $output_file generated and ready for Linux."
} else {
puts "--> CRITICAL ERROR: The file $input_file was not found!"
puts " Check if the '-bin_file' option is checked in Bitstream settings."
}
- Save this file in your project folder (where the
.xpris) with the name**generate_bin.tcl**.
Step 2: Configure the “Hook” in Vivado
Now let’s tell Vivado to run this script whenever it finishes generating the bitstream.
- In the Flow Navigator panel (on the left), click on Settings (under Project Manager).
- In the window that opens, go to the Bitstream category.
- Look for the field called tcl.post.
- Click on the … button (browse) and select the
generate_bin.tclfile you just created. - Click OK to save.

Step 3: The Final Test
Now, click on Generate Bitstream again.
If everything goes well, Vivado will generate the normal bitstream and, immediately after, will execute your script silently. You should see the leds_linuxx.bin file appear in the project folder (usually inside impl_1 or in the root, depending on where the script ran).
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- post_id
- a9cb3ec0a114
- slug
- fpga-on-red-pitaya-series-5-5-automating-vivado-with-tcl-scripts-a9cb3ec0a114
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- https://medium.com/@alanfr.engel/fpga-on-red-pitaya-series-5-5-automating-vivado-with-tcl-scripts-a9cb3ec0a114
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- https://medium.com/@alanfr.engel/fpga-on-red-pitaya-series-5-5-automating-vivado-with-tcl-scripts-a9cb3ec0a114
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- status
- ok
- fetched_at
- 2026-07-15 20:50:45