Coherent Samples 300mm SiC for AI Chips [Semiconductor News, Aug 19, 2026]

Today’s 3-Line Summary

• Coherent has begun customer sampling of 300mm high thermal conductivity SiC substrates for AI chips. (GlobeNewswire)
• Manz Asia is rolling out panel-level RDL production equipment supporting 310, 510 and 700mm panels, positioned as production-proven. (PR Newswire)
• Nikon’s “Litho Booster 1000” for 3D semiconductors improves wafer measurement accuracy by roughly 35%. (MONOist)

1. Coherent Moves 300mm High Thermal Conductivity SiC Substrates for AI to Customer Evaluation, Improving Heat Dissipation by up to 25%

On August 17 at 4:05 p.m. Eastern Time, Coherent announced that it had begun sampling 300mm high thermal conductivity SiC (silicon carbide) substrates for AI semiconductors to its key AI chip partners. In Japan time that is 5:05 a.m. on August 18, which falls inside the last 24 hours. (GlobeNewswire)

These SiC substrates are aimed at something a little different from the SiC normally used as a substrate for EV power semiconductors.

What Coherent has in mind is use as a heat dissipation material for AI processors and HPC semiconductors.

In AI processors, power consumption and heat density are rising sharply, and it is no longer just raw compute performance that matters. How efficiently the generated heat can be moved out of the package increasingly determines both performance and reliability.

According to Coherent, these 300mm SiC substrates are designed to improve heat dissipation performance by up to 25% compared with current solutions, while maintaining compatibility with existing semiconductor manufacturing platforms. (GlobeNewswire)

Coherent is vertically integrated across SiC crystal growth, wafer processing, polishing and characterization.

With this customer sampling, the 300mm SiC platform moves from internal development into actual evaluation by AI chipmakers. It is an important step toward eventual volume production. (GlobeNewswire)

Going to 300mm matters too.

In the semiconductor industry, most advanced logic and memory is manufactured on 300mm wafers. If the heat dissipation material can also move to 300mm, it becomes far easier to align with existing high-volume manufacturing infrastructure.

Key points: customer sampling of 300mm high thermal conductivity SiC substrates has started; the target application is thermal management for AI and HPC chips; heat dissipation performance is improved by up to 25% versus current solutions; Coherent is vertically integrated from SiC crystal growth through polishing and characterization; the platform has moved from internal development to the customer evaluation phase.

Quick comment

When people hear SiC, EV power semiconductors usually come to mind first. But this application is not “SiC that controls power,” it is “SiC that carries heat away.”

As AI chip power consumption keeps climbing, raising transistor performance alone is not enough. If the heat cannot escape, that performance cannot be sustained.

The point of this news is that the competition has moved beyond liquid cooling and cold plates, into changing the materials sitting right next to the die in order to improve heat dissipation.

Together with the idea of matching existing semiconductor manufacturing infrastructure at 300mm, this deserves attention as a new market for advanced packaging materials aimed at AI. (GlobeNewswire)

Source: Coherent Begins Customer Sampling of 300mm High Thermal Conductivity Silicon Carbide Substrates for AI Infrastructure (GlobeNewswire)

2. Manz Asia Supports Panels up to 700mm, Rolling Out RDL Production Equipment for Advanced AI Packaging

On August 18, Manz Asia announced ECD (electrochemical deposition) and wet process equipment for advanced semiconductor packaging, supporting panel sizes of 310mm, 510mm and 700mm.

The announcement was made at 9:00 a.m. Eastern Time on August 18, which is 10:00 p.m. the same day in Japan, again inside the 24-hour window. (PR Newswire)

Manz Asia’s “Omni 310,” “Omni 510” and “Omni 700” are equipment platforms that integrate multiple wet processes such as cleaning, developing, etching and stripping around the ECD step required to build RDL (redistribution layers).

What stands out is support for large panels up to 700mm.

In advanced packaging today, the mainstream approach is to form RDL and interposers on 300mm wafers. But AI chips bundle GPUs, ASICs and HBM into a single package, and package sizes are growing rapidly.

Manz Asia argues that this growth is driving a shift from the 300mm wafer approach to Panel-Level Packaging, which uses panels with far more usable area. (PR Newswire)

Beyond FOPLP (Fan-Out Panel-Level Packaging), the Omni series also supports CoPoS and TGV (Through-Glass Via) for glass core substrates.

For glass, it handles substrates up to 0.4mm thick, minimum 20 micrometer fine vias, and TGV formation at aspect ratios up to 1:20. It also brings copper plating by ECD that fills high aspect ratio vias without voids. (PR Newswire)

According to Manz Asia, the 310mm, 510mm and 700mm RDL platforms are all “production-proven,” meaning equipment with a track record in actual volume production use. (PR Newswire)

Key points: support for 310, 510 and 700mm panels; ECD, cleaning, developing, etching and stripping integrated into one platform; support for FOPLP, CoPoS and glass core TGV; TGV down to 20 micrometers with aspect ratios up to 1:20; aimed at volume production of large packages for AI and HPC.

Quick comment

In advanced packaging for AI, the area needed to carry GPUs and HBM keeps growing.

The problem here is the physical size of the 300mm wafer.

The larger the rectangular package you cut out of a round wafer, the more unusable area you leave behind at the edges.

That is why Panel-Level Packaging, which builds RDL on large rectangular panels from the start, is drawing attention.

The arrival of production-capable equipment reaching 700mm is interesting because it shows that the very assumption of “building packages on wafers” is starting to change because of AI. (PR Newswire)

Source: Manz Asia Pioneers Production-Proven 310/510/700 mm ECD and Wet Process Solutions for Panel-Level Packaging (PR Newswire)

3. Nikon’s Alignment Station for 3D Semiconductors: 35% Better Measurement Accuracy, 10% Higher Throughput

MONOist reported on Nikon’s new alignment station “Litho Booster 1000” at 1:00 p.m. on August 18.

The Litho Booster 1000 sits alongside a semiconductor lithography tool and measures wafer distortion and positional deviation with high precision before exposure. It is scheduled for release in January 2027. (MONOist)

The new model improves the wafer holder structure, reducing the error that occurs when the wafer is chucked.

As a result, measurement accuracy is roughly 35% better than the previous model. (MONOist)

The measurement light source has also been strengthened, making alignment marks and overlay marks easier to detect.

The wafer transfer robot and transport mechanism were improved as well, lifting throughput by about 10%. It also handles heavily warped wafers. (MONOist)

This matters most for 3D semiconductor manufacturing such as W2W (Wafer to Wafer) bonding.

When wafers are bonded together, stress creates distortion in the wafer. If the next layer is exposed in that state, the wiring and structures on the upper and lower layers will not connect accurately unless positions are corrected at the nanometer level.

By measuring distortion across the entire wafer in advance with the Litho Booster 1000 and passing that correction data to the lithography tool, high-precision overlay becomes possible in the next exposure step. (MONOist)

3D structures are spreading from CMOS image sensors to NAND and logic, and wider use in DRAM is expected going forward.

Key points: measurement accuracy improved roughly 35% versus the previous model; throughput improved about 10%; support for heavily warped wafers; high-precision measurement of distortion after W2W bonding; release scheduled for January 2027.

Quick comment

In 3D semiconductors, the job does not end at “bonding wafers cleanly.”

After bonding, the wafer is not perfectly flat. Heat and stress make it stretch and shrink slightly.

To expose the next layer in that state, you have to measure distortion across the whole wafer and use that data to correct exposure positions.

As stacked structures multiply, in 3D NAND, stacked logic and future 3D DRAM, the importance grows not only of the lithography tool itself but of the equipment that accurately measures the wafer’s condition just before it. (MONOist)

Source: Nikon’s alignment station improves wafer measurement accuracy by about 35% (MONOist, in Japanese)

My Take

What does “25% better” actually mean?

On August 17, Coherent announced it had begun sampling 300mm high thermal conductivity SiC substrates for AI and HPC to its key AI semiconductor partners. The applications are next-generation heat spreaders and related packaging, and the company says heat spreading performance improves by up to 25% compared with “current solutions.” It also emphasizes vertical integration, doing crystal growth, wafer processing, polishing and characterization in house.

That 25%, though, deserves a little caution. The release only says “current solutions,” and never specifies what the 25% is being measured against. Nor do we yet know how many degrees the temperature actually drops in a real AI package, or how much that translates into clock speed, reliability or cooling cost. At this point it is strictly the customer evaluation stage.

Even so, the framing is easy to grasp: as AI chips keep generating more heat, the ability to remove that heat has itself become a constraint on system performance. I think the heart of this news is heat.

In fact, 300mm SiC is not new here. Coherent had already announced a 300mm SiC platform in December 2025, with thermal efficiency in AI data centers as the primary application. Even then, data center thermal management was the main use case, with AR/VR and power electronics listed as separate applications. So this announcement is not a new material. It should be read as a milestone marking the move from internal development to customer evaluation.

SiC is hard. But hard alone does not make money.

What concerns me here is the conventional SiC substrate business.

According to TrendForce, the N-type SiC substrate market in 2024 was 1.04 billion dollars, down 9% year over year. Wolfspeed led with 33.7%, but Chinese players surged, with TanKeBlue at 17.3% and SICC at 17.1%, while Coherent slipped from its prior ranking to fourth at 13.9%. Those two Chinese companies alone account for 34.4%.

Growing high-quality SiC single crystals is not easy. Crystal defects, warpage, processing and yield are all difficult problems.

But unlike leading-edge logic, this is not the kind of wall where “you cannot enter unless you can obtain an EUV lithography tool.” Put in enough time and capital, build up the technology, and Chinese makers can come in. The result is a technology that is difficult and yet oversupplied, and in the end it gets ground down on price. The fact that intense competition and steep price declines drove revenue down in the 2024 SiC substrate market shows exactly how dangerous that is.

Sumitomo Electric is another telling example. The company has the technology to commercialize its 6-inch SiC single crystal substrate “CrystEra” and has worked across substrates and epitaxy. In June 2023 its SiC wafer volume production plan was certified under METI’s stable supply assurance program, but it later withdrew that production plan in response to shifting EV demand and changes in the business environment around SiC. With that, the METI certification, and up to 10 billion yen in expected subsidies, was cancelled as well.

This gives us reason to treat “being able to make SiC” and “being able to make money from SiC” as two different things.

So I think it is significant that Coherent has brought 300mm SiC to AI thermal management rather than to power semiconductors.

Coherent has light

What makes this more interesting is that Coherent is not merely a SiC materials company.

At OFC 2026 it showed 6.4T CPO using silicon photonics, an External Laser Source using its own InP CW lasers, VCSEL-based CPO, and an InP modulator on silicon operating at 400G. In other words, SiC, InP lasers, silicon photonics and CPO all live inside the same company.

As CPO advances, optical devices get placed right next to switch ASICs and future AI processors. The closer you bring electrical and optical together, the more important it becomes to work out how high-heat logic and optical devices can coexist.

If this high thermal conductivity SiC becomes not just a heat spreader for GPUs but a thermal platform underpinning future optoelectronic packages, the story changes considerably.

Coherent has of course not announced anything that far. From here on it is my speculation.

Still, given that both optical and thermal materials and device technologies exist within the same company, I think there is ample room to combine them in the future.

How not to fight China on “price per SiC wafer”

If they can get to that shape, the axis of competition changes too.

On 300mm SiC substrates alone, Chinese players will eventually catch up, and there is a real chance of entering the same price war as conventional SiC. But if SiC is built into the thermal design of CPO and AI packages, and the company works its way into customer designs across InP, silicon photonics, bonding and assembly, then a cheap SiC substrate showing up is not enough to replace it easily.

Interestingly, Sumitomo Electric also holds not only SiC crystal growth technology but heterogeneous integration of InP and silicon photonics, optical connection components for CPO, and Cu-diamond heat spreaders for semiconductor lasers.

And yet even Sumitomo Electric pulled back from new volume production investment in SiC wafers.

I think this is the important part.

The competitor to watch from here may not be the company that can simply make SiC substrates in volume, but the company that can bundle light, heat and materials under one roof and work its way into the design of AI systems.

I do not believe Chinese companies cannot make 300mm SiC. It is better to assume they eventually will.

Which is exactly why what Coherent needs is to get into AI chipmakers’ and CPO designs before that happens, and to stop selling “SiC substrates” and instead become part of a thermal design that cannot easily be swapped out.

The up to 25% improvement in heat spreading performance announced this time may be the entrance to that.

Is Coherent aiming to sell 300mm SiC at a high price? Or to combine SiC with its own optical technologies and move into territory where a simple price fight with Chinese players is harder to start?

I am watching the latter possibility.

Wrap-up

Today’s three stories show that AI and 3D semiconductors are raising the importance of technologies that were not previously seen as the main characters of the industry.

Coherent is trying to use 300mm SiC as a heat dissipation material to carry heat away from AI processors. SiC’s applications are expanding beyond power semiconductors into thermal management for AI chips. (GlobeNewswire)

At Manz Asia, equipment has appeared that builds RDL in volume on panels up to 700mm, in response to ever larger AI packages. The traditional size constraint of the 300mm wafer is being pushed past from the packaging side. (PR Newswire)

And Nikon has strengthened technology that measures wafer distortion after W2W bonding with high precision and hands the correction values to the next exposure step. The further 3D stacking goes, the harder measurement and alignment become. (MONOist)

Lined up together, today’s news makes it visible that competition in AI semiconductors is spreading beyond raw transistor performance into the technologies of moving heat out, connecting across larger areas, and stacking accurately.