FPGAs for Absolute Beginners: Your First Project in Vivado using NEXYS A7

Welcome, future hardware designers! If you’re an engineering student starting your journey into the world of Field-Programmable Gate Arrays (FPGAs), you’ve landed in the right place. This article will guide you through your very first lab session, where we’ll bring a simple digital circuit to life using the powerful Xilinx Vivado Design Suite.

We’ll start from absolute zero: creating a project, writing our first lines of Verilog code, simulating the design, and finally, programming an FPGA board to see our creation work in the physical world. So let’s get right away!

What is an FPGA?

Before we jump into the tools, let’s quickly understand what we’re working with. A Field-Programmable Gate Array (FPGA) is a fascinating piece of silicon. Unlike a regular microprocessor (like in your laptop) which has a fixed function, an FPGA is a blank slate. You can program its internal circuitry to act as any digital system you can imagine — a simple logic gate, a complex processor, or anything in between.

Think of it as a digital Lego set where you can define how each block connects to others, all after the chip has been manufactured. We use a language called Verilog HDL (Hardware Description Language) to “tell” the FPGA what we want it to become. There are several computing industries which define different kinds of FPGA boards, the one we are going to use is NEXYS A7.

NEXYS A7 FPGA Trainer Board

The Five-Step Journey of an FPGA Design

In Vivado, transforming your Verilog code into a functioning circuit on the FPGA involves five key steps:

1. Synthesis: Vivado converts your human-readable Verilog code into a netlist of basic logic gates.
2. Mapping: This gate-level netlist is then mapped to the specific components (like Look-Up Tables or LUTs) available on the target FPGA.
3. Placing: The tool decides the optimal physical locations on the FPGA for these mapped components to minimize delays and use space efficiently.
4. Routing: The programmable connections (wires) inside the FPGA are configured to link all the placed components together.
5. Bitstream Generation: Finally, the placed and routed design is converted into a .bit file, a binary stream that contains all the configuration information for the FPGA.

Loading this bitstream onto the board programs the FPGA to behave as per your design.

Hands-On: Building a Simple AND Gate

For this tutorial, our goal is simple: implement a 2-input AND gate on a Nexys A7 FPGA board. An AND gate outputs a ‘1’ only when both of its inputs are ‘1’.

Step 1: Creating a New Project in Vivado

1. Fire up the Vivado IDE. You’ll be greeted by a start screen.

Xilinx Project Navigator Window

1. Click “Create Project” under Quick Start. A wizard will guide you.
2. Choose a name for your project and a location.
3. Select “RTL Project” as the project type. RTL stands for Register Transfer Level, a common way to design digital circuits.
4. In the ‘Add Sources’ window, we can choose to create HDL files here or later after setting up the project. Let’s skip it for now.
5. Same goes for adding constraint file as well, we’ll come back to it later.
6. In the ‘Default Part’ window, you need to select these options for implementing design on NEXYS A7 board:

• Family: Artix-7
• Device: xc7a100t
• Package: csg324
• Speed Grade: -1

7. Review the summary and click Finish. Your project is now created!

Step 2: Writing the Verilog Code

After setting up the project, the main editor window will appear.

Main window

Now, let’s describe our AND gate in Verilog.

1. In the ‘Sources’ window, click the “+” icon and select “Add or create design sources”.
2. Click “Create File”, name it according to your preference (eg: MyANDgate ) and set the file type to Verilog.
3. A new window will pop up for you to define the module’s ports (its inputs and outputs). You can skip it as you’ll have to define this in the code itself or fill it in as follows:

• Port Name: a, Direction: in
• Port Name: b, Direction: in
• Port Name: c, Direction: out

4. Click OK and Finish. Vivado will generate a template for you.

5. In the ‘Sources’ panel, double-click MyANDgate.v to open it. A typical AND gate verilog code should look like this:

module myANDgate(
    input a,
    input b,
    output c
    );

    and o1(c, a, b); // This is a built-in Verilog primitive for an AND gate

endmodule

Step 3: Simulating the Design

Before we program the board, it’s wise to check if our logic works correctly. We do this with a testbench.

1. Click “Add Sources” again, but this time choose “Add or create simulation sources”.
2. Create a new file named “test”.
3. Open this file and paste the following testbench code. This code applies all possible input combinations (00, 01, 10, 11 ) to our AND gate.

module test1;
    // Inputs
    reg a;
    reg b;
    // Outputs
    wire c;
    // Instantiate the Unit Under Test (UUT)
    MyANDgate uut (
        .a(a),
        .b(b),
        .c(c)
    );
    initial begin
        // Initialize Inputs
        a = 0; b = 0; #100; // Wait for 100 time units
        a = 1; b = 0; #100;
        a = 1; b = 1; #100;
        a = 0; b = 1; #100;
        a = 1; b = 1; #100;
    end
endmodule

4. Save the file. Now, in the flow navigator on the left, go to Simulation > Run Simulation > Run Behavioral Simulation

5. A waveform window will open, showing you how the outputs change over time as the inputs change. Verify that output c is '1' only when both a and b are '1'.

Simulating the design

Bringing the Design to Life on the FPGA

This is the most exciting part! We will now connect our virtual design to the physical pins of the FPGA.

Step 4: Adding the Constraints File

The Nexys A7 board has physical switches and LEDs. We need to tell Vivado that input a is connected to a specific switch, and output c is connected to a specific LED. We do this with a Constraints File (.xdc).

1. Click “Add Sources”, select “Add or create constraints”, and name your file.
2. Open this file and add the following lines:

## Switches
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports a];
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports b];
## LEDs
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports c];

This code maps port a to switch *0* (pin J15), port b to switch *1* (pin L16), and port c to LED 0 (pin H17).

Step 5: Generating the Bitstream and Programming the Board

We’re almost there!

1. In the Flow Navigator, click “Generate Bitstream”. Vivado will run Synthesis, Implementation, and finally generate the .bit file. This might take a minute.
2. Now, connect your Nexys A7 board to your computer via USB and turn it on.
3. In Vivado, open “Hardware Manager” and click “Open Target” > “Auto Connect”.
4. Once your board is detected, click “Program Device”. A dialog will pop up with the path to your .bit file.
5. Click “Program”.

Bit file path

If all goes well, you’ll see a success message in the console.

Step 6: Testing on the Real Hardware

The moment of truth! On your Nexys A7 board:

• Flip switch 0 (assigned to input a ) and switch 1 (assigned to input b ).
• Watch LED 0 (assigned to output c ).

The LED will light up only when both switches are in the ON (up) position. Congratulations! You have successfully designed, simulated, and implemented a digital system on an FPGA.