From Code to Circuit: 4-Bit Full Adder on Nexys A7 FPGA

Have you ever wondered how computers perform binary addition so effortlessly? Behind every arithmetic operation lies a fundamental building block of digital electronics — the Full Adder.

In this post, I’ll walk you through how I designed and tested a 4-bit Full Adder on the Nexys A7–100T FPGA board using Verilog HDL.

How Full Adder Works

It takes in three inputs:

• A → the first binary bit
• B → the second binary bit
• Cin → the carry input (from the previous stage)

And it gives two outputs:

• S (Sum) → represents the binary sum of the three inputs
• Cout (Carry Output) → represents the carry generated from this addition

1-bit Full Adder Circuit

4-bit Full Adder Circuit

Truth Table of Full Adder

Mathematically, Sum = A ⊕ B ⊕ C COUT = (A & B) | (B & C) | (A & C)

Logic Behind the Design

The 4-bit full adder is designed by cascading four single-bit full adders. Each adder receives inputs A[i], B[i], and a carry from the previous stage.

module full_Adder( 
  input A, 
  input B, 
  input C, 
  output SUM, 
  output COUT
);

wire a1, a2, a3;

xor u1(a1,A,B);
and u2(a2,A,B);
and u3(a3,a1,C); 
or u4(COUT,a2,a3);
xor u5(SUM,a1,C);

endmodule  // single bit Adder

module four_bit_full_adder(
 input [3:0] A,
 input [3:0] B,
 input C,
 output COUT,
 output [3:0] SUM
);
wire C1,C2,C3;

full_Adder i1(.A(A[0]), .B(B[0]), .C(C), .COUT(C1), .SUM(SUM[0]));
full_Adder i2(.A(A[1]), .B(B[1]), .C(C1), .COUT(C2), .SUM(SUM[1]));
full_Adder i3(.A(A[2]), .B(B[2]), .C(C2), .COUT(C3), .SUM(SUM[2]));
full_Adder i4(.A(A[3]), .B(B[3]), .C(C3), .COUT(COUT), .SUM(SUM[3]));
endmodule

Pin Configuration

The XDC file serves as a constraint file that defines how logical signals in the design are mapped to the physical pins of the Nexys A7 board. The snippet below shows the relevant pin mappings used in this project:

## Inputs on switches
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { C }];
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { B[0] }];
set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { B[1] }];
set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { B[2] }];
set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { B[3] }];
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { A[0] }];
set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { A[1] }];
set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { A[2] }];
set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { A[3] }];

## Outputs on LEDs
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { SUM[0] }];
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { SUM[1] }];
set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { SUM[2] }];
set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { SUM[3] }];
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { COUT }];

Switches (A, B, and C) act as binary inputs, while LEDs display the SUM and COUT outputs.

Testing on the Nexys A7 Board

After synthesizing and generating the bitstream file, I programmed the FPGA board and observed the results through the onboard LEDs. To verify the design, here’s the series of steps for testing.

Step 1: Take Inputs

A = 1011 
B = 1010 
Cin = 1 (carry-in)

Step 2: Align the Bits

  1011 
+ 1010 
+ 1

Step 3: Add Bit by Bit

Step 4: Result

Sum = 0110 
Cout = 1

LED output on Nexys A7 for input A=1011, B=1010, Cin=1

This project demonstrates how simple digital logic scales into meaningful hardware behavior. Implementing a 4-bit full adder using Verilog HDL and FPGA hardware offers an insightful look into the modular nature of arithmetic circuits.

It’s a small yet powerful step toward understanding how hardware computation truly comes alive.