Asynchronous and Synchronous Reset in an FSM

Upon reset, an FSM defaults to the IDLE state. Reset mechanisms are broadly classified into two types: synchronous reset and asynchronous reset.

A synchronous reset is sampled only during the active clock edge. It is generally considered safer because it reduces the likelihood of the FSM entering incorrect or illegal states. The time between the assertion of reset and the next clock edge helps ensure that the reset signal has propagated to all state flip-flops before they sample it. This is particularly beneficial in large FSMs where reset signal skew may exist. As a result, all state flip-flops sample the reset on the same clock event, leading to deterministic reset behavior.

An asynchronous reset, on the other hand, does not depend on a clock edge. It acts immediately once asserted and can therefore provide rapid initialization or fault recovery. In systems where immediate response is critical, asynchronous resets are often preferred. However, they are also more susceptible to hazards that can cause the FSM to enter incorrect or illegal states.

Due to reset distribution skew, different state flip-flops may observe the asynchronous reset at different times. This can temporarily produce unintended state encodings before all state bits reach the intended reset state. For example, consider an FSM with 9 states encoded using 4 flip-flops. The valid state encodings range from 0000 (0) to 1000 (8), and the reset state is 0000.

Suppose the FSM is currently in state 0111 when an asynchronous reset is asserted. If reset skew temporarily causes only the first two flip-flops to be reset, the state register may momentarily assume the encoding 0011. If a clock edge occurs before all state bits have reached the intended reset value 0000, the FSM may evaluate its next state using the incorrect state encoding 0011. This would result in an incorrect state transition.

An illegal state is a special case of an incorrect state. It occurs when the FSM enters a state encoding that is not part of the intended design space. For example, if the FSM encoding spans from 0000 (0) to 1000 (8), but the FSM reaches 1011 (11), then 1011 is an illegal state.

Reset deassertion is generally considered even more sensitive than reset assertion in asynchronous reset designs. In fact, incorrect and illegal states are more likely to occur during reset release. For example, after the FSM has reached the reset state 0000, the first two flip-flops may exit reset before the remaining two. During this interval, a clock edge may cause the first two flip-flops to transition to the next state while the remaining flip-flops are still held in reset. This can result in an unintended state encoding and potentially cause the FSM to enter an incorrect or illegal state.

In a synchronous reset scheme, both reset assertion and deassertion are recognized only on a clock edge. Consequently, all state flip-flops observe the reset transition on the same clock event, significantly reducing the likelihood of such hazards.

Therefore, careful consideration must be given when selecting the reset strategy for an FSM, as the choice directly affects the reliability and predictability of the design.