Ternary Computing: The way classical computing should be designed

Authors: Kevin McNamara and Rhea Pritham Marpu

Abstract — Ternary computing represents a paradigm shift from conventional binary systems, utilizing three discrete states per digit rather than two. This paper examines the theoretical foundations, historical development, architectural principles, and future prospects of ternary computing systems. With information density 58% higher than binary per digit (log2(3) ≈ 1.585 bits per trit) and inherent advantages in arithmetic operations, ternary computing offers compelling solutions for emerging challenges in artificial intelligence, energy-efficient computing, andneuromorphic systems. We analyze the mathematical optimality grounded in radix economy, review historical implementations from Setun to modern carbon nanotube-based prototypes, and evaluate contemporary applications in AI acceleration and IoT devices. Our analysis reveals that while ecosystem barriers remain significant, recent advances in material science and AI optimization create favorable conditions for ternary adoption in specialized domains, with over 120 IEEE publications in 2020-2024 indicating sustained research momentum.

Index Terms — ternary computing, multi-valued logic, balanced ternary, radix economy, carbon nanotube transistors, AI acceleration, neuromorphic computing

I. INTRODUCTION

Modern computing infrastructure relies almost exclusively on binary (base-2) logic, where information is encoded as bits representing two states: 0 and 1. Ternary computing challenges this paradigm by introducing a third state, creating trits (ternary digits) that can represent 0, 1, and 2 in unbalanced systems, or -1, 0, and +1 in balanced systems [1]. This additional state enables each trit to carry approximately log2(3)≈1.585 bits of information, providing a 58% improvement in information density per digit [2].

The theoretical foundation for ternary computing’s efficiency stems from radix economy — a metric quantifying the cost of representing numbers as the product of the base and required digits [3]. Among integer bases, base-3 achieves the lowest radix economy, closely approximating Euler’s number e (≈2.718), which minimizes representation cost in continuous systems [4]. This mathematical optimality suggests ternary systems naturally align with efficiency principles observed throughout nature, from exponential growth patterns to neural information processing.

A. Terminology and Key Concepts

Before proceeding with technical analysis, we establish the nomenclature used throughout this paper. The fundamental unit of ternary information is the trit, analogous to the binary bit. Collections of trits form larger units: a tryte typically comprises 6 trits (equivalent to approximately 9.5 bits), providing a convenient grouping for ternary word sizes. Ternary systems manifest in two principal forms. Balanced ternary employs digit values {-1, 0, +1}, offering symmetric representation around zero without requiring separate sign bits — a significant advantage for arithmetic operations. Conversely, unbalanced ternary uses digit values {0, 1, 2}, maintaining partial compatibility with binary systems by sharing the 0 and 1 states.

Contemporary ternary research heavily leverages advanced materials and devices. Carbon Nanotube Field-Effect Transistors (CNTFETs) utilize carbon nanotubes as channel material, enabling precise threshold voltage control essential for multi-valued logic implementation. Memristors — two-terminal passive components with variable resistance that persists without power — provide natural three-state storage capabilities ideal for ternary memory architectures.

In quantum computing, the ternary analog to the qubit is the qutrit, a quantum system with three orthogonal basis states. In neural network optimization, Ternary Weight Networks (TWNs) constrain weights to {-1, 0, +1}, enabling extreme model compression and efficient hardware implementation through elimination of complex multiply operations. These concepts form the technical vocabulary underlying ternary computing’s theoretical advantages and practical implementations, which we explore throughout subsequent sections.

B. Radix Economy: A Concrete Example Consider representing the decimal number 100,000:

• In binary (base-2), this requires 17 digits (1 1000 01101010 00002), yielding a radix economy of 2 ×17 = 34.

• In ternary (base-3), only 11 digits are needed (11 22012021 03), producing a radix economy of 3 ×11 = 33 — demonstrating measurable efficiency gains [5].

To quantify the practical benefits of ternary representation across different value ranges, Table I compares the number of digits required and the resulting efficiency gains.

Figure 1 illustrates how radix economy varies with the choice of number base, demonstrating why base-3 is mathematically optimal among integer bases.Fig. 1. The theoretical cost of number representation, or radix economy, plotted against the choice of base (radix). The cost is minimized at the continuous base of Euler’s number, e ≈ 2.718. Among integers, base-3 is closest to this optimal point, providing the most efficient number representation. This mathematical principle is the theoretical foundation for the superior information density of ternary computing.

To visualize the information density advantage of ternary systems, Figure 2 provides a graphical comparison of how binary and ternary digits encode information.

Despite theoretical advantages, ternary computing has re-mained largely relegated to academic research due to binary’s entrenched ecosystem and simpler hardware implementation.

However, as Moore’s Law approaches physical limits [6] and applications demand more efficient computation — particularly in AI, IoT devices, and neuromorphic computing — ternary systems are experiencing renewed interest.

II. HISTORICAL DEVELOPMENT

A. Early Mechanical Systems (19th Century)

The concept of ternary computation predates electronic computers. In 1840, English inventor Thomas Fowler constructed a mechanical calculating machine using balanced ternary arithmetic for tax and interest calculations [7]. Fowler’s machine, built primarily from wood, demonstrated that nonbinary computation was mechanically feasible, though it remained a curiosity without widespread adoption.

B. Electronic Ternary Computing (1950s–1970s)

The electronic computing era brought renewed interest in ternary logic. In 1958, Nikolay Brusentsov at Moscow State University developed Setun, the first modern electronic ternary computer [8]. Named after a nearby river, Setun operated on balanced ternary logic and demonstrated remarkable efficiency advantages:

• 50% reduction in component count compared to equivalent binary machines

• Lower power consumption through reduced switching activity

• More efficient signed arithmetic without requiring separate sign bits

Table II catalogs the major ternary computing implementations throughout history, showing their evolution from mechanical calculators to modern electronic systems. Setun’s Arithmetic: In Setun’s balanced ternary system, subtraction of 5–3 was performed by negating 3 (which simply flips all + and — signs, yielding -3) and adding: 5 + (-3)= 2. This eliminated the complex two’s complement operations required in binary systems [9].

Detailed Addition Example: Consider adding +5 and +3 in balanced ternary (positions: 9s, 3s, 1s):

• +5 = 9–3–1 →+−−

• +3 = 3 →0+0

Adding column by column (right to left):

1. 1s position:−+ 0 =−

2. 3s position:−+ + = 0

3. 9s position: + + 0 = +

Result: +0−= 9(1) + 3(0) + 1(-1) = 9–1 = 8 = 5 + 3

An improved version, Setun-70, was developed in 1970 with enhanced capabilities. Meanwhile, Western efforts included the Ternac emulator (1973, United States) and the QTC-1 computer (Canada), though these systems remained experimental[10].

C. Decline and Binary Dominance (1970s–2000s)

By the mid-1970s, the rapid commoditization of binary integrated circuits created overwhelming economic advantages for binary systems. The principal challenge facing ternary adoption was state detection complexity: while binary systems distinguish two states using a single voltage threshold, ternary systems require two thresholds to separate three states [11].

Figure 3 illustrates the fundamental difference in voltage level requirements between binary and ternary systems, highlighting the noise margin challenges inherent in three-state logic.

For practical CMOS implementation, designers must carefully assign voltage levels to represent the three states while maintaining adequate noise margins. Table III shows typical voltage level assignments for a 3.3V supply.

State Detection Example: In a 5V binary system, voltages below 2.5V might represent ‘0’ and above 2.5V represent ‘1’ — a single comparison. Ternary systems require voltages near 0V for ‘-1’, near 2.5V for ‘0’, and near 5V for ‘+1’, demanding two threshold comparisons (e.g., <1.5V, 1.5–3.5V, >3.5V). Electronic noise and manufacturing variance made

TABLE III

CMOS TERNARY VOLTAGE LEVELS (3.3V SUPPLY)

Logic State Balanced Voltage Range Nominal

Low (-) -1 0V — 0.8V 0V

Middle (0) 0 1.2V — 2.1V 1.65V

High (+) +1 2.5V — 3.3V 3.3V

reliable three-state detection significantly more challenging than binary’s robust two-state logic [12]. This technical barrier, combined with the absence of a commercial ecosystem, relegated ternary computing to academic research for decades.

D. Contemporary Revival (2010s–Present)

The 21st century has witnessed renewed interest driven by:

• Material science advances: Carbon Nanotube Field-Effect Transistors (CNTFETs) enable reliable three-state operation [13]

• Memristor technology: Three-state resistive memory devices suit ternary logic [14]

• AI optimization needs: Neural network quantization aligns naturally with ternary weights {-1, 0, +1}[15]

• Moore’s Law constraints: As binary transistor scaling slows, alternative paradigms gain attention [16] Research institutions such as the University of South-Eastern Norway (USN) Ternary Research Group have maintained continuous ternary logic investigation for over a decade, contributing open-source tools and educational resources [17].

III. THEORETICAL FOUNDATIONS

A. Mathematical Optimality and Radix Economy The efficiency of ternary representation derives from radix economy, defined as R ×⌈logR(N )⌉, where R is the base and N is the number to represent [18]. This metric quantifies the “cost” of representing numbers by considering both the base complexity and digit count.

For continuous bases, radix economy is minimized at e ≈2.718. Among integer bases, base-3 is closest to e, providing optimal efficiency [19]. The practical implication is that ternary systems require fewer total “digit-state” combinations to represent equivalent numeric ranges.

Detailed Storage Comparison: To store numbers 0–728 (729 unique values):

• Binary: Requires ⌈log2(729)⌉ = 10 bits. 210 = 1,024 states (295 unused states = 28.7% inefficiency).

• Ternary: Requires ⌈log3(729)⌉= 6 trits. 36 = 729 states (0% waste — exact fit).

• Efficiency gain: 6 trits vs. 10 bits = 40% fewer storage elements

This represents a significant reduction in physical memory requirements and demonstrates ternary’s superior information density for this range.

B. Information Density

Information theory quantifies a trit’s capacity as log2(3) ≈1.585 bits [2]. This means:

• 6 trits ≈9.51 bits of information capacity

• 27 trits ≈42.8 bits (more than 42 bits can hold)

This density advantage becomes more pronounced in larger systems, potentially reducing memory requirements and interconnect complexity [20].

C. Balanced vs. Unbalanced Ternary

Balanced Ternary {-1, 0, +1}:

• Symmetric around zero

• Negation is trivial: flip + to — and vice versa

• No separate sign bit needed

• Ideal for arithmetic-intensive applications

Unbalanced Ternary {0, 1, 2}:

• Partial compatibility with binary (shares 0 and 1 states)

• Can leverage semiconductor leakage currents

• Suited for hybrid binary-ternary interfaces

Multiplication by -1 Example: To multiply +7 by -1 in balanced ternary:

• Convert 7 to balanced ternary: 7 = 9–3 + 1 →+−+ (positions: 9s, 3s, 1s)

• Multiply by -1: Simply flip all signs: +−+ becomes−+−

• Verification:−+−= -9 + 3–1 = -7

Comparison to Binary: In 4-bit two’s complement, 7 is 01112. To get -7:

1. Invert bits: 0111 →1000

2. Add 1: 1000 + 0001 = 1001

Result: 10012 = -7 in two’s complement. The ternary advantage is a single sign-flip operation versus two operations in binary.

IV. COMPREHENSIVE BINARY VS. TERNARY COMPARISON

To provide a holistic view of the differences between binary and ternary computing, Table IV presents a side-by-side comparison across multiple dimensions, from fundamental information representation to practical implementation considerations.

V. TERNARY LOGIC OPERATIONS

A. Logic Gate Fundamentals

Ternary logic gates operate on three-valued truth tables. For two-input operations, this creates 3×3 = 9 input combinations, compared to binary’s 2×2 = 4 combinations. The number of possible two-input ternary functions is 39 = 19,683, vastly exceeding binary’s 24 = 16 functions [21].

B. Core Ternary Gates

Using balanced ternary notation {-, 0, +}where — = -1, 0 = 0, + = +1:

MIN Gate (Ternary AND): Returns the minimum value based on ordering < 0 < +.

MAX Gate (Ternary OR): Returns the maximum value.

NOT Gate (Negation): Simple inversion: + →-, — →+, 0 →0. This enables trivial arithmetic negation.

TNAND Gate (Antiminimum): Inverts MIN output (+ ↔-, 0 unchanged). TNAND is functionally complete.

The complete truth tables for the fundamental ternary logic operations are presented in Tables V–VIII, showing how these gates operate on all possible input combinations in balanced ternary notation.

Table IX quantifies the hardware implementation overhead of ternary gates compared to binary equivalents across different fabrication technologies.

C. Arithmetic Operations

Ternary addition utilizes SUM (addition mod 3) and CARRY gates. A ternary half-adder produces sum and carry from two trit inputs. To illustrate ternary arithmetic operations and their efficiency compared to binary, Table X presents representative examples.

Adding Two Trits:

• (+1) plus 0 (0): Result is + (SUM: +1, CARRY: 0)

• (+1) plus + (+1): Result is — with a carry of + (SUM: -1,

CARRY: +1) [since 1+1 = 2 = -1 + 1×3]

Multiplication is simpler than binary in some cases due to symmetric representation. Multiplying by -1 is simply negation (sign flip), unlike binary which requires two’s complement subtraction.

D. Hardware Implementation Complexity

While ternary gates carry more information, they require more complex circuits:

• Binary XOR:∼8–12 CMOS transistors

• Ternary SUM:∼11–14 CMOS transistor pairs [22]

However, CNTFETs can implement ternary gates more efficiently through controlled threshold voltage engineering, potentially achieving transistor counts comparable to binary gates [23].

CNTFET Ternary Inverter: A CNTFET-based ternary inverter can be constructed with 4 transistors by using CNTs of different diameters to set distinct threshold voltages for three-state operation, whereas a CMOS implementation might require 6–8 transistors for equivalent noise margins [24].

VI. ADVANTAGES OF TERNARY COMPUTING

A. Superior Information Density Each trit encodes∼1.585 bits (∼58% more data per digit).

A 64-trit register holds∼101.4 bits of capacity, equivalent to a 102-bit binary register. This can reduce memory addressing and interconnect density [25].

B. Energy Efficiency

Ternary systems reduce switching activity and dynamic power. The historical Setun consumed∼20% less power than comparable binary computers [26], and modern CNT-based ternary adders project 30–40% energy reduction [27].

Table XI compares projected power consumption across different implementation technologies, demonstrating the energy efficiency advantages of ternary systems.

C. Simplified Signed Arithmetic

Balanced ternary eliminates sign bits and complex two’s complement operations. Negation is a simple inversion, making subtraction a trivial operation of “add the negative” [9].

D. Error Detection Capabilities

The middle state (0) can represent “unknown” or “undefined,” enabling inherent error detection. An unexpected ‘0’ can signal a potential error or uninitialized variable without extra hardware [28].

E. AI and Machine Learning Optimization

Ternary Weight Networks (TWNs) use weights {-1, 0, +1}, reducing model size by∼5×and enabling “zero-skipping” to eliminate multiply operations, drastically improving hardware efficiency [15], [29]. Neural Network Weight Encoding Example: For a neural network layer with 1,000 neurons:

• 32-bit Floating Point: 1,000 weights ×32 bits/weight

= 32,000 bits. Requires complex floating-point multiply units.

• Ternary Weight Network: 1,000 weights ×1 trit/weight. In binary encoding: 1,000 weights ×2 bits/trit = 2,000 bits. Memory reduction: 16×compared to FP32.

Hardware Operation: For input x and ternary weight w:

• If w = +1, output = x (pass through, no multiplication)

• If w = 0, output = 0 (skip computation entirely)

• If w =−1, output =−x (simple negation)

This approach eliminates floating-point multipliers, massively reducing chip area, power consumption, and latency.

VII. CHALLENGES AND LIMITATIONS

A. Hardware Implementation Complexity Distinguishing three voltage levels requires two threshold comparators and results in tighter noise margins, increasing susceptibility to thermal noise, crosstalk, and manufacturing variations [30].

B. Design Considerations

Area: Ternary gates occupy∼2–3×the area of binary gates in CMOS, but closer to∼1.2–1.5×with CNTFETs due to natural multi-threshold operation.

Power: Dynamic power can be reduced by∼30–40% due to fewer state transitions and the ability to skip computations when weights are zero.

Speed: Propagation delay is∼1.2–1.8×slower in CMOS due to intermediate state settling time. CNTFETs can achieve comparable speeds to binary due to superior electron mobility.

C. Ecosystem and Standardization

Binary computing benefits from decades of optimized compilers, libraries, EDA tools, and commodity components. Ternary systems lack this infrastructure, creating high adoption barriers.

To evaluate which computing domains are most suitable for ternary versus binary implementations, Table XII assesses various application areas based on their alignment with each paradigm’s strengths.

D. Software Toolchain Requirements Compilers need modifications for new data types, overloaded operators, and specific optimization passes. A proposed

C extension might look like:

E. Transition Costs

Migrating to ternary involves redesigning ISAs, rewriting billions of lines of software, and retraining engineers. These switching costs are economically prohibitive without a massive performance incentive.

F. Potential Transistor Count Overhead

While algorithmically efficient, gate-level implementations can require more transistors (e.g., a binary NAND uses 4 transistors vs. 12–16 for a CMOS ternary TNAND) [31]. Advanced materials can mitigate this but add risk.

VIII. MODERN IMPLEMENTATIONS AND RESEARCH

A. Material Science Advances

Carbon Nanotube Field-Effect Transistors (CNTFETs):

CNTs with precisely controlled diameters exhibit distinct threshold voltages, enabling natural three-state operation. Stanford University demonstrated a CNTFET-based ternary processor with 97% functional yield [32].

Memristors: Three-state resistive memory devices naturally map to ternary logic. Memristor-based ternary neural networks show promise for neuromorphic computing [33].

Memristor Storage Example: A memristor with three stable resistance states (e.g., 1kΩ, 10kΩ, 100kΩ) can directly store a trit, whereas binary memristor systems require multiple devices or more complex analog sensing circuits to achieve the same.

B. Recent Prototypes and Tools

South Korean Unbalanced Ternary Semiconductor (2019): Researchers developed a ternary inverter using conventional silicon technology, demonstrating manufacturability without exotic materials [34].

USN Ternary Research Group: This group provides opensource EDA tools for mixed-radix circuits, memristor controller designs, and ternary logic simulators [35].

Commercial Efforts: Conceptual designs like the 5500FP ternary floating-point processor, high-speed binary-ternary interface circuits, and software emulators for ternary ISAs are emerging [36].

C. Publication Trends

Between 2020–2024, over 100 IEEE papers addressed ternary logic gates using carbon nanotube technology, indicating sustained research momentum [37]. Key application domains include:

• Low-power IoT devices

• Neuromorphic computing systems

• Cybersecurity (ternary public-key cryptography)

• Robotics (ternary control systems)

To track the evolution of ternary computing research interest over time,

Table XIII summarizes publication activity and major technological breakthroughs across different periods.

IX. APPLICATION-SPECIFIC USE CASES

To demonstrate the practical benefits of ternary computing in real-world scenarios, we present three detailed application examples:

A. IoT Sensor Node

An environmental sensor with a strict energy budget could see a 33% power reduction by using a 6-trit microcontroller instead of an 8-bit one.

This translates to:

• Battery life: Potentially 50% increase from 2 years to 3 years on a single coin cell

• Data transmission: More efficient encoding reduces wireless transmission time and energy

• Processing efficiency: Simplified arithmetic reduces computation cycles

B. AI Edge Inference Accelerator

For image classification on an edge device, a Ternary Weight

CNN can achieve:

• Model compression: 8×reduction in model size

• Power reduction: 60% lower power consumption compared to 8-bit quantized network

• Accuracy trade-off: Typical accuracy loss of 1–3% on ImageNet classification

• Inference speed: 3–5× faster due to elimination of multiply operations

C. Secure Communication System

Ternary public-key cryptography uses ternary polynomial rings for key generation, creating novel mathematical structures that:

• May be resistant to some quantum attacks (post-quantum cryptography)

• Provide different security assumptions than binary elliptic curve or RSA systems

• Enable more compact key representations in certain applications

X. FUTURE PROSPECTS

A. Research Roadmap

The path forward for ternary computing involves coordinated efforts across multiple research domains. We outline key priorities organized by timeframe:

1. Near-Term Priorities (2025–2028): Standardization:

• Form IEEE working group for ternary logic standards

• Develop standard ISA specifications for ternary processors

• Create reference implementations and benchmarks EDA Tool Development:

• Ternary logic synthesis tools

• Place-and-route algorithms optimized for ternary gates

• Timing analysis and power estimation tools

• Verification and simulation frameworks

Compiler Infrastructure:

• LLVM backend for ternary targets

• Optimization passes for ternary arithmetic

• Type systems supporting ternary data types

2. Medium-Term Objectives (2028–2035): Manufacturing:

• Foundry processes for CNTFET ternary logic with >95% yield

• Development of ternary SRAM and DRAM technologies

• High-volume manufacturing cost reduction

System Integration:

• Heterogeneous binary-ternary processors

• Memory hierarchies optimized for ternary data

• Interconnect protocols supporting ternary signaling

B. Near-Term Applications (2025–2030)

AI Accelerators: Ternary neural network accelerators for edge computing, leveraging ternary weight networks for 5× model compression and energy reduction [15].

IoT Devices: Low-power ternary microcontrollers for sensor networks where energy efficiency is critical and computational complexity is moderate.

Cryptography: Ternary public-key systems offering novel security properties distinct from binary implementations [38].

C. Long-Term Vision (2035+)

Paradigm Shift Applications:

• Fully ternary data centers with specialized AI workloads

• Qutrit-based quantum computers leveraging three-level quantum systems

• Optical ternary networks using three polarization or phase states

• Neuromorphic computing systems natively operating in ternary

Optical Ternary Computing: Fiber-optic ternary logic using three polarization or phase states, potentially achieving THz switching speeds with minimal thermal dissipation [39].

Quantum Ternary Computing: Qutrits (three-state quantum systems) offering theoretical advantages over qubits for certain quantum algorithms, though requiring new error-correction schemes [40].

Josephson Junction Ternary Memory: Superconducting devices with three flux states for ultra-low-power cryogenic computing systems [41].

D. Open Research Questions

• What is the optimal memory hierarchy design for ternary systems?

• Can ternary logic provide inherent advantages for quantum error correction?

• How can we create economically viable binary-to-ternary migration paths?

• What novel algorithms emerge when ternary operations are primitive?

E. Expert Perspectives

Computer scientist Donald Knuth, creator of TeX and author of The Art of Computer Programming, has advocated for ternary computing’s mathematical elegance, suggesting it may resurge as binary limitations become acute [42]. The convergence of material science advances, AI optimization needs, and energy constraints creates favorable conditions for ternary adoption in specialized domains.

XI. CONCLUSION

Ternary computing represents a theoretically superior alternative to binary systems, offering 58% higher information density per digit, simplified arithmetic operations, and inherent error detection capabilities. Its mathematical optimality grounded in radix economy minimization near Euler’s constant e — suggests alignment with natural efficiency principles.Historical barriers including hardware complexity, ecosystem inertia, and three-state detection challenges have limited adoption.

However, 21st-century advances in carbon nanotube transistors, memristive devices, and AI-driven optimization are revitalizing ternary research. With over 100 recent IEEE publications and working prototypes achieving high functional yields, ternary computing is transitioning from academic curiosity to practical consideration.

Near-term applications in AI acceleration, IoT devices, and specialized cryptography appear promising. Long-term prospects encompass optical and quantum ternary systems potentially disrupting conventional computing paradigms. While wholesale replacement of binary infrastructure remains unlikely, ternary computing may establish niches where its advantages prove decisive — particularly as Moore’s Law constraints intensify and energy efficiency becomes paramount.

Continued investment in ternary-specific EDA tools, standardization efforts, and manufacturing processes will determine whether ternary computing achieves mainstream adoption or remains a specialized alternative for targeted applications.

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Despite theoretical advantages, ternary computing has re-