4-bit universal decimal to SSD (Seven-Segment Display) counter.

External View of the System

Introduction

Design and implement a 4-bit universal decimal counter using VHDL, which will display the output on a seven-segment display (SSD). This type of counter is commonly used in digital systems for counting purposes where the result needs to be easily read by humans. The goal of this project is to showcase skills in VHDL design, simulation, and the application of advanced digital design tools.

Design Brief

The designed 4-bit universal decimal counter must fulfil the following key functionalities.

· Synchronous Parallel Load (PL): Allows the counter to load a specific value synchronously.

· Parallel Data Input (PD3, PD2, PD1, PD0): Inputs for parallel data to be loaded into the counter.

· SSD Outputs (S6, S5, S4, S3, S2, S1, S0): Outputs corresponding to the segments A through G of the seven-segment display.

· Asynchronous Reset Input (RST): An input that resets the counter asynchronously, setting the SSD output to zero.

· Count Direction (CD): An input that determines the counting direction, enabling the counter to count up or down.

· Synchronising Clock Input (CLK): A clock signal that synchronises the counting process.

This design requires careful consideration of digital design principles and VHDL programming to ensure accurate and efficient counter operation. The report will cover the entire design process, from the initial design brief to the final simulation results, providing a comprehensive overview of the counter’s development and functionality.

function table and design

Solution Explanation

External View of the 4-bit universal decimal to SSD (Seven-Segment Display) counter.

External View of the System

The designed SSD counter has five inputs and one output. When designing this counter, four states are used: IDEAL, A, B, and C. The IDEAL state is the starting state. If the input RST=0 is given in any state, the state changes to IDEAL. State A is the Up-counter state, State B is the Down-counter state, and State C is the free state. In State C, the counter can transition to any state freely, and any number can be output given the input for PD.

State Diagram of the System

VHDL Code Listing

VHDL Implementation

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity test01 is

port (

CLK: in STD_LOGIC; — clock signal RST: in STD_LOGIC; — Asynchronous Reset Input PL: in STD_LOGIC; — Synchronous Parallel Load CD: in STD_LOGIC; — Count direction(Up/Down) PD: in STD_LOGIC_VECTOR (3 downto 0); — Parallel Data Input SSD_OUT: out STD_LOGIC_VECTOR (6 downto 0) — SSD outputs seven segment display

);

end test01;

architecture Behavioral of test01 is

type SSD_FSM is (IDEAL, A, B, C);

signal Count: STD_LOGIC_VECTOR(3 downto 0) := “0000”; — 4-bit count number

signal current_state, next_state: SSD_FSM := IDEAL;

begin

Process(CLK, RST)

begin

if RST = ‘0’ then

current_state <= IDEAL;

elsif rising_edge(CLK) then

current_state <= next_state;

end if;

end process;

Process(current_state, PL, CD, PD)

begin

if RST = ‘1’ then

case current_state is

— Ideal State

when IDEAL =>

if PL = ‘0’ and CD = ‘1’ then

next_state <= A;

elsif PL = ‘0’ and CD = ‘0’ then

next_state <= B;

elsif PL = ‘1’ then

Count <= PD;

next_state <= C;

end if;

— Up Counter

when A =>

if PL=’0' and CD = ‘1’ then

if Count = “1001” then

Count <= “0000”;

else

Count <= Count + 1;

end if;

next_state <= A;

elsif PL = ‘0’ and CD = ‘0’ then

if Count = “0000” then

Count <= “1001”;

else

next_state <= B;

end if;

elsif PL = ‘1’ then

Count <= PD;

next_state <= C;

end if;

— Down Counter

when B =>

if PL = ‘0’ and CD = ‘0’ then

if Count = “0000” then

Count <= “1001”;

else

Count <= Count — 1;

end if;

next_state <= B;

elsif PL = ‘0’ and CD = ‘1’ then

if Count = “1001” then

Count <= “0000”;

else

next_state <= A;

end if;

elsif PL = ‘1’ then

Count <= PD;

next_state <= C;

end if;

— Synchronous Data Load

when C =>

if PL = ‘1’ then

Count <= PD;

next_state <= C;

elsif PL = ‘0’ and CD = ‘1’ then

if Count = “1001” then

Count <= “0000”;

else

next_state <= A;

end if;

elsif PL = ‘0’ and CD = ‘0’ then

if Count = “0000” then

Count <= “1001”;

else

next_state <= B;

end if;

end if;

end case;

else

next_state <= IDEAL;

Count <= “0000”;

end if;

end process;

— Related Count values for SSD_OUT

Process(Count)

begin

case Count is

when “0000” => SSD_OUT <= “0111111”; — 0

when “0001” => SSD_OUT <= “0000110”; — 1

when “0010” => SSD_OUT <= “1011011”; — 2

when “0011” => SSD_OUT <= “1001111”; — 3

when “0100” => SSD_OUT <= “1100110”; — 4

when “0101” => SSD_OUT <= “1101101”; — 5

when “0110” => SSD_OUT <= “1111101”; — 6

when “0111” => SSD_OUT <= “0000111”; — 7

when “1000” => SSD_OUT <= “1111111”; — 8

when “1001” => SSD_OUT <= “1100111”; — 9

when others => SSD_OUT <= “0000000”; — Blank or error state

end case;

end process;

end Behavioral;

Testbench Code

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY main_tb IS

END main_tb;

ARCHITECTURE behavior OF main_tb IS

— Component Declaration for the Unit Under Test (UUT)

COMPONENT test01

PORT(

CLK : IN std_logic;

RST : IN std_logic;

PL : IN std_logic;

CD : IN std_logic;

PD : IN std_logic_vector(3 downto 0);

SSD_OUT : OUT std_logic_vector(6 downto 0)

);

END COMPONENT;

— Inputs

signal CLK : std_logic := ‘0’;

signal RST : std_logic := ‘0’;

signal PL : std_logic := ‘0’;

signal CD : std_logic := ‘0’;

signal PD : std_logic_vector(3 downto 0) := (others => ‘0’);

— Outputs

signal SSD_OUT : std_logic_vector(6 downto 0);

— Clock period definitions

constant CLK_period : time := 10 ns;

BEGIN

— Instantiate the Unit Under Test (UUT)

uut: test01 PORT MAP (

CLK => CLK,

RST => RST,

PL => PL,

CD => CD,

PD => PD,

SSD_OUT => SSD_OUT

);

— Clock process definitions

CLK_process : process

begin

while true loop

CLK <= ‘0’;

wait for CLK_period/2;

CLK <= ‘1’;

wait for CLK_period/2;

end loop;

end process;

— Stimulus process

stim_proc: process

begin

— Hold reset state for 100 ns.

RST <= ‘0’;

PL <= ‘0’;

CD <= ‘0’;

wait for 100 ns;

— Release reset

RST <= ‘1’;

wait for CLK_period*10;

— Test counting up (counting up 10 clock cycles)

PL <= ‘0’;

CD <= ‘1’;

wait for CLK_period*10;

— Test counting down (counting down 10 clock cycles)

PL <= ‘0’;

CD <= ‘0’;

wait for CLK_period*10;

— Test Parallel load with value 3

PL <= ‘1’;

PD <= “0011”; — Load 3

wait for CLK_period*10;

PL <= ‘0’; — Clear PL to allow counting

wait for CLK_period*10;

— Test Parallel load with value 6

PL <= ‘1’;

PD <= “0110”; — Load 6

wait for CLK_period*10;

PL <= ‘0’; — Clear PL to allow counting

wait for CLK_period*10;

— Test counting up again (counting up 10 clock cycles)

PL <= ‘0’;

CD <= ‘1’;

wait for CLK_period*10;

— Test counting down again (counting down 10 clock cycles)

PL <= ‘0’;

CD <= ‘0’;

wait for CLK_period*10;

— Test Reset

RST <= ‘0’;

wait for 100 ns;

RST <= ‘1’;

wait;

end process;

END;

In this Testbench code test following steps

· Hold reset state for 100 ns. · Release reset. · Test counting up (counting up 10 clock cycles). · Test counting down (counting down 10 clock cycles). · Test Parallel load with value 3. · Test Parallel load with value 6. · Test counting up again (counting up 10 clock cycles). · Test counting down again (counting down 10 clock cycles). · Test Reset.

Graphical Testbench Screenshot

Simulated results

Simulation Results

The simulation results for the 4-bit universal decimal to Seven-Segment Display (SSD) counter are presented to demonstrate the functionality and correctness of the VHDL design. The results highlight several key operational modes and transitions of the counter, including counting up, counting down, parallel loading, and asynchronous resetting. Here’s a detailed explanation of the simulation results.

Counting Up

The counter begins in the idle state and transitions to the up-counting state when the count direction (CD) input is set to ‘1’. With each rising edge of the clock signal (CLK), the counter increments its value by one. The SSD outputs (SSD_OUT) display the corresponding decimal digit on the seven-segment display, ranging from 0 to 9. When the counter reaches the value ‘9’, it wraps around to ‘0’.

Counting Down

The counter transitions to the down-counting state when the count direction (CD) input is set to ‘0’. With each rising edge of the clock signal (CLK), the counter decrements its value by one. The SSD outputs (SSD_OUT) display the corresponding decimal digit on the seven-segment display, ranging from 9 to 0. When the counter reaches the value ‘0’, it wrapsaround to ‘9’.

Parallel Load

When the parallel load (PL) input is set to ‘1’, the counter transitions to the parallel load state. The value specified by the parallel data input (PD) is then loaded into the counter, and the SSD outputs (SSD_OUT) immediately display the loaded value on the seven-segment display. After loading, the counter can resume counting up or down based on the count direction (CD) input.

Asynchronous Reset

The counter transitions to the idle state when the asynchronous reset (RST) input is set to ‘0’. The counter value is reset to ‘0’, and the SSD outputs (SSD_OUT) display ‘0’ on the seven-segment display. The reset operation is immediate and independent of the clock signal (CLK). The simulation results confirm that the VHDL code works correctly, showing that the counter behaves as expected under different conditions. The counter accurately counts up and down, properly loads data, and resets when needed. The seven-segment display shows the correct numbers for each counter value, proving that the counter and display logic are well-integrated and functioning as intended.

Conclusions

This design is crucial for various industrial applications. Seven-segment displays are widely used to provide a user-friendly numeric display in devices such as instrumentation panels, measurement devices, and digital clocks. A 4-bit counter can efficiently represent decimal numbers from 0 to 9, making it suitable for applications requiring single-digit numeric displays. This is particularly beneficial in embedded systems where space and power are limited. In industrial environments, real-time data display is essential for monitoring and control. A 4-bit counter driving a seven-segment display can offer immediate visual feedback for processes such as counting, timing, and measuring. During the design process, several challenges were encountered. Errors in the state transition diagram can cause the counter to skip states, become stuck, or transition incorrectly. Misinterpretation of binary to decimal encoding can lead to incorrect digit representation. Additionally, bugs in the VHDL code that controls the counter and display logic can result in incorrect counting or display. The design can be improved by extending it to multiple seven-segment displays, which would enhance its utility in industrial applications.