STM32F1 NVIC Interrupt Management

Let’s go step by step and summarize how NVIC interrupt management works in STM32F1 (Cortex-M3 core):

1. NVIC Basics

• The Nested Vectored Interrupt Controller (NVIC) is part of the ARM Cortex-M3 core.
• It manages external interrupts (IRQ) and exceptions (like SysTick, HardFault).
• STM32F1 devices support up to 60+ interrupt vectors, depending on the model.

2. Interrupt Vector Table

• Stored in Flash at address 0x0800 0000 (or relocated to SRAM if configured).
• Each entry holds the start address of the interrupt handler function.
• Handlers are declared as C functions, e.g.:

void EXTI0_IRQHandler(void) {
    // Your code for EXTI Line0 interrupt
}

3. Enabling NVIC Interrupts

Interrupts are controlled in two steps:

1. Peripheral-level enable (configure the specific peripheral, e.g., EXTI, USART, TIM).
2. NVIC-level enable using CMSIS functions:

NVIC_EnableIRQ(EXTI0_IRQn);   // Enable EXTI line 0 interrupt
NVIC_DisableIRQ(EXTI0_IRQn);  // Disable

• Each *_IRQn is defined in stm32f10x.h.

4. Priority Management

• STM32F1 NVIC supports 4 bits of priority → 16 priority levels (0 = highest, 15 = lowest).
• Use:

NVIC_SetPriority(EXTI0_IRQn, 5);   // Set EXTI0 interrupt priority to 5

• Priorities define preemption: lower number = higher priority.
• If two interrupts have the same priority, the one with the lower IRQ number wins.

5. Nested Interrupts

• If a high-priority interrupt occurs during a lower-priority ISR, NVIC preempts the running ISR.
• Cortex-M3 automatically saves context (registers) to the stack, so you don’t need special prologue/epilogue assembly code.

6. Pending & Active States

• Each interrupt has three states: Pending, Active, Inactive.
• Software can manually trigger interrupts:

NVIC_SetPendingIRQ(EXTI0_IRQn);   // Force interrupt
NVIC_ClearPendingIRQ(EXTI0_IRQn); // Clear pending flag

• Useful for testing or triggering ISRs without hardware events.

7. Interrupt Masking

• Globally disable interrupts:

__disable_irq();   // Disable all IRQs
__enable_irq();    // Re-enable

• For finer control, use PRIMASK (all interrupts except NMI and HardFault) or FAULTMASK (disables all except NMI).

8. Best Practices

• Keep ISRs short and fast — offload heavy work to the main loop or an RTOS task.
• Always clear the interrupt flag inside ISR, or it will retrigger endlessly.

if (EXTI_GetITStatus(EXTI_Line0) != RESET) {
    // Handle interrupt
    EXTI_ClearITPendingBit(EXTI_Line0);  // Clear flag
}

• Avoid calling printf() or blocking functions inside ISRs.

Summary: On STM32F1, the NVIC provides priority-based, nested interrupt management. You enable interrupts both in the peripheral and NVIC, assign priorities, and keep ISRs efficient. Cortex-M3 hardware simplifies nesting by automatically handling stack saving/restoring.