Why I stopped using JTAG for field debugging

Spent the last 6 months moving everything over to SWD and honestly don’t know why I held onto JTAG for so long. The pin count alone should have been enough reason. 4 pins vs 2 on a board where every trace matters.

The real issue was the tooling. Most of the JTAG adapters I was using were overkill for what I actually needed. Running boundary scan on a cortex-m4 is like bringing a logic analyzer to read a GPIO pin. SWD does everything I need for runtime inspection and flash programming and the physical footprint on the PCB is way smaller.

Had one project last year where the JTAG header was physically too large for the enclosure revision and we had to do a board spin just to move it. That was the last straw. Now everything gets a 10 pin SWD header with a Tag Connect footprint and we haven’t had a clearance issue since.

The one exception is multicore stuff where you need daisy chaining. SWD doesn’t handle that well and probably won’t. So the old Segger J-Link stays in the drawer for those cases. But for single core ARM work there’s no reason to stick with JTAG in 2026 unless your workflow is built around it and you don’t want to change.

Which is fine. But at least admit that’s the reason instead of pretending JTAG gives you something SWD doesn’t for 90% of use cases.