A recommended layout guideline for placing a crystal oscillator on an STM32-based PCB

Here’s a recommended layout guideline for placing a crystal oscillator on an STM32-based PCB, along with a simple top-view diagram to visualize the correct placement.

Crystal Oscillator Placement Guidelines for STM32

1. Place Close to MCU

• The crystal should be placed as close as possible to the STM32’s OSC_IN and OSC_OUT pins.
• Short trace lengths reduce parasitic capacitance and inductance, improving signal quality and startup reliability.

2. Keep Traces Short and Symmetrical

• Route the crystal signal traces short, direct, and of equal length.
• Avoid long loops or stubs to reduce EMI and phase shift.

3. Use Grounded Guard Ring (optional)

• Surround the crystal and traces with a grounded copper pour (guard ring) to reduce EMI and crosstalk.

4. Avoid Noisy Areas

• Don’t place the crystal near switching regulators, inductors, or high-speed digital lines (e.g., USB, SPI).

5. Dedicated Ground Pad

• If possible, provide a dedicated ground via near the load capacitors and crystal for a clean return path.

🖼️ Top-View Placement Diagram

pgsql

+--------------------------------------------+
|                                            |
|         STM32 MCU                          |
|       +-----------------+                  |
|       |                 |                  |
|       |   OSC_IN   o----|----------------+ |
|       |                 |                | |
|       |   OSC_OUT  o----|-----+          | |
|       +-----------------+     |          | |
|                               |          | |
|                              +-+         | |
|                              | | Crystal | |
|                              +-+         | |
|                               |          | |
|                         +-----+-----+    | |
|                         | Load Caps |    | |
|                         +-----------+    | |
|                               |          | |
|                            GND VIA       | |
|                                            |
+--------------------------------------------+

Additional Layout Tips

• Use load capacitors (C1 and C2) according to the crystal’s datasheet (typically 12–22pF).
• Keep crystal traces on the top layer to avoid via-induced inductance.
• Place a ground plane underneath the crystal and related traces.
• Don’t route high-speed or noisy traces under or near the crystal circuit.