HUM SOC TCH CS csjo logicion wire vs reg in Verilog: A Beginner’s Guide to Choosing the Right Data Type If you have just started learning Verilog, there is a good chance your very first compiler error looked something like “illegal reference…
TCH SPT CS csjo logicion FSM Design 101: Building a Traffic Light Controller in Verilog Every traffic light you have ever waited at is running a tiny program. It cycles through a fixed set of conditions — green, then yellow…
CS csjo logicion Metastability in FPGA Design: The Hidden Danger Every Beginner Should Understand If you’ve worked with FPGAs for a while, you’ve probably encountered a strange kind of bug: your design works in simulation, passes timing…
CS csjo logicion Verilog vs VHDL: Which HDL Should You Learn First? A friendly, side-by-side comparison for beginners stepping into FPGA and ASIC design.
CS csjo logicion What is UVM? A Gentle Introduction for Beginners Picture this: a verification engineer is staring at thousands of lines of simulation logs, trying to figure out why a single signal…
CS csjo logicion Building a UART Transmitter in Verilog: Step by Step A Beginner’s Guide to Sending Serial Data from Your FPGA
CS csjo logicion Building a Simple ALU in Verilog: A Beginner’s Guide to Arithmetic and Logic Operations Every processor you have ever used, from the chip in your laptop to the tiny microcontroller in your microwave, has a small but mighty…
ART CS csjo logicion Moore vs Mealy State Machines in Verilog: A Beginner’s Guide to Choosing the Right FSM Style If you’ve ever built a traffic light controller or a vending machine in Verilog, you’ve already used a Finite State Machine (FSM). But…
MDA CS csjo logicion Implementing a FIR Filter in Verilog: A Beginner’s Guide to FPGA Digital Signal Processing If you have ever used the “smoothing” feature on a graph, blurred a photo, or removed hiss from an audio recording, you have already met a…
CS csjo logicion FPGA Power Optimization Techniques: A Beginner’s Guide Every FPGA engineer has had that moment: you boot up your brand-new design, touch the chip, and quickly pull your finger back. “Why is it…
TCH CS csjo logicion AXI Bus Protocol in FPGA Design: A Beginner’s Guide to ARM’s On-Chip Interconnect If you’ve spent any time exploring modern FPGA or SoC design, you’ve probably bumped into three letters that show up everywhere: AXI…
CS csjo logicion Inferred Latches in Verilog: A Beginner’s Guide to Avoiding This Hidden FPGA Bug Imagine you ask Verilog to describe a multiplexer, but somehow you end up with a tiny piece of memory you never wanted. That little…
CS csjo logicion PWM Generation in Verilog: A Beginner’s Guide to Dimming LEDs and Driving Motors Have you ever wondered how a single digital pin that can only output a 0 or a 1 manages to dim an LED smoothly or spin a motor at half…
TCH CS csjo logicion I2C Protocol in FPGA Design: A Beginner’s Guide to Inter-Integrated Circuit If you’ve ever wondered how chips talk to each other inside a smartphone, a sensor module, or an FPGA development board, you’ve already met…
TCH CS csjo logicion Binary to BCD Conversion in Verilog: A Beginner’s Guide to the Double Dabble Algorithm You have built a counter on your FPGA and wired it to a seven-segment display. You expect to see the number 42, but the display shows…
CS csjo logicion Round-Robin Arbiters in Verilog: A Beginner’s Guide to Fair Resource Sharing When several parts of your FPGA design all want the same thing at once, someone has to decide who goes first, and how to keep it fair…
CS csjo logicion Seven-Segment Display Driver in Verilog: A Beginner’s Guide to Multiplexed Displays If blinking an LED was your “Hello, World!” on an FPGA, then lighting up a seven-segment display to show a real number is your first proper…
ART CS csjo logicion Gray Code Counters in Verilog: A Beginner’s Guide to Glitch-Free Counting If you’ve ever built a binary counter in Verilog, you’ve already met one of digital design’s quietest troublemakers: multiple bits flipping…
CS csjo logicion Verilog case Statements: A Beginner’s Guide to Multiplexers and Decoders If you’ve been following this series, you’ve already built counters, shift registers, and even an LFSR. All of those designs rely on making…
CS csjo logicion Barrel Shifters in Verilog: A Beginner’s Guide to Fast Multi-Bit Shifting Imagine you need to shift a number left by 5 positions. With a regular shift register, you’d clock it five times, moving one bit per cycle…
CS csjo logicion Ready/Valid Handshaking in Verilog: A Beginner’s Guide to Reliable Data Transfer Imagine two people passing notes in class. One person writes a note and holds it out, but the other can only take it when their hands are…
CS csjo logicion Clock Dividers in Verilog: Generating Slower Clocks the Right Way If you have ever tried to blink an LED on an FPGA board, you have probably hit an awkward mismatch: your board’s clock ticks 50 or 100…
CS csjo logicion Parameterized Modules in Verilog: A Beginner’s Guide to Writing Reusable Hardware If you’ve been building counters, shift registers, and FIFOs in Verilog, you’ve probably noticed something annoying: every time you need an…
MDA CS csjo logicion Shift Registers in Verilog: A Beginner’s Guide to Moving Data Bit by Bit Imagine a line of people passing buckets of water from one end to the other. Each second, every person hands their bucket to the neighbor…
CS csjo logicion Tri-State Buffers in Verilog: A Beginner’s Guide to High-Impedance Outputs If you have ever wondered how multiple devices can share a single data bus without crashing into each other, the answer is tri-state…