#system-verilog

Eight Green Formal Proofs Became Five Fileable Ones When I Audited the SystemVerilog Assertions

Building a synthetic tape-out sign-off board changed my view of what an AI-authored SVA proof has to show before review.

AXI-Lite to Wishbone Converters Pt. 1: Foundations

Recently, as part of a chip-design club, I worked with a team of digital design engineers to build an AXI-Lite to Wishbone converter module…

The Silent Bottleneck in Chip Design Nobody Talks About Enough

Everyone loves talking about chip design. Architecture diagrams, clever pipelines, power optimization tricks. It’s the fun part. But ask…

FPGA On FPGA

Hello Reader,

Learning UVM with me Day 2

Day 2 學習目標

The Complete Guide to Hardware Pipeline Design with Backpressure: Ready/Valid Handshake Explained

Pipelining is the first tool most hardware engineers reach for when a design cannot meet its timing target. Splitting a long computation…

Learning UVM with me Day 1

請chatgpt幫我規畫學習UVM的基礎

From Verilog to SystemVerilog — Day 4

1. Randomization

Parsing NASDAQ ITCH on an FPGA

Your computer is too slow to read the stock market. No, I don’t mean the internet. It’s your computer itself.

Why FSimX Built Its Own SystemVerilog Front End

We started FSiMX with Slang. But today, FSiMX runs on its own SystemVerilog front end and elaboration engine.

Ready/Valid Handshake Explained : How Hardware Handles Data Flow and Backpressure

Constraint Random Verification: Finding Bugs You Never Expected

Introduction

From Verilog to SystemVerilog — Day 3

1. Task

From Verilog to SystemVerilog — Day 2

Packed vs Unpacked Array

From Verilog to SystemVerilog — Day 1

System Verilog跟Verilog有一些差別，以下就開始入門System Verilog吧。

The Hardest Part of UVM Is Not the Testbench. It’s the Scoreboard.

Everyone focuses on the wrong thing.

Before UVM, We Were Just Guessing

Verification used to look like this…

Breaking the Windows/Linux Barrier: Native FPGA Design on Apple Silicon

For years, being a hardware designer with a Mac felt like a curse.

Synchronous FIFO Design & Verification: What Actually Went Wrong

Building a FIFO is one of those things that feels straightforward — until you simulate it.

What is UVM? A Gentle Introduction for Beginners

Picture this: a verification engineer is staring at thousands of lines of simulation logs, trying to figure out why a single signal…

Advanced UVM — Coverage, Constraints & Reusable VIPs

// VLSI · Design Verification · UVM Series — Part 3

Building Your First UVM Testbench from Scratch

// VLSI · Design Verification · UVM Series — Part 2

How Pipelined CPUs are Designed

In this article, I’ll go over how to design a pipelined processor. The processor implements a Hennessy & Patterson-style MIPS RISC…

Solving SystemVerilog Fragmentation Across EDA Tools

DashRTL v2025.12 solves SV fragmentation by offering a SV compatiblity feature to identify compatibility issues across EDA tools

Introduction to Hardware Description Languages

Abstract

Cross-Tool Compatibility Issues of SystemVerilog Designs

SV RTL cross-tool compatibility remains a challenge; unsupported syntax may force extra iterations. DashRTL offers a full solution.

Understanding AXI4 Burst Transactions with Flow Control: A Case Study

In this article, we will delve into the inner workings of AXI4 burst transactions, specifically focusing on a scenario where an…

Mastering Verilog: Implementing a Half Adder.

In this blog post, we’ll focus on implementing a Half Adder in Verilog. The Half Adder is a fundamental building block in digital circuits…

My journey of Google Summer of Code 2023.

I recently had the incredible opportunity to participate in Google Summer of Code (GSoC) program, collaborating with MERL (Micro Electronic…

Synchronous FIFO Tester Using Cocotb

Recently I installed cocotb on my computer and tried the examples provided in the cocotb package under examples folder. The examples…

Google Summer of Code: Week 1

This post describes my progress and work in the first week of Google Summer of Code '18. I'm engaged in a project related to Hardware…