Moore vs Mealy State Machines in Verilog: A Beginner’s Guide to Choosing the Right FSM Style

If you’ve ever built a traffic light controller or a vending machine in Verilog, you’ve already used a Finite State Machine (FSM). But there’s a design choice hiding inside every FSM that beginners often skip past: should it be a Moore machine or a Mealy machine? Getting this right affects your timing, your outputs, and even whether your design has glitches.

In this guide, we’ll break down both styles in plain language, compare them side by side, and write real Verilog for each. By the end, you’ll know exactly which one to reach for.

A Quick Refresher: What Is an FSM?

A Finite State Machine is a circuit that remembers where it is. It has a set of states, and it moves between them based on inputs. Think of a turnstile: it’s either Locked or Unlocked, and a coin or a push moves it from one state to the other. Every FSM has three pieces working together.

• A state register: the flip-flops that hold the current state.
• Next-state logic: decides which state comes next.
• Output logic: decides what the outputs should be.

The Moore vs Mealy question is entirely about that last piece: how the outputs are generated.

Moore Machines: Outputs Depend Only on State

In a Moore machine, the outputs depend only on the current state, not on the inputs directly. Each state has a fixed output. When you are in a given state, the output is whatever that state dictates, no matter what the inputs happen to be doing right now.

Here is a helpful analogy: a Moore machine is like a room with a sign on the door. The sign only changes when you walk into a different room. Whatever is happening in the hallway outside does not change the sign until you actually move.

Because outputs only change when the state changes on a clock edge, Moore outputs are clean and glitch-free. The trade-off is that they can react one clock cycle later than a Mealy machine. Below is a Moore-style detector for the serial bit pattern “101”.

// Moore FSM: detects the serial pattern "101"
module seq_detect_moore (
    input  wire clk,
    input  wire rst,
    input  wire din,
    output reg  detected
);
    localparam S_IDLE = 2'b00; // seen nothing
    localparam S_1    = 2'b01; // seen "1"
    localparam S_10   = 2'b10; // seen "10"
    localparam S_101  = 2'b11; // seen "101"

    reg [1:0] state, next;

    // State register (sequential)
    always @(posedge clk) begin
        if (rst) state <= S_IDLE;
        else     state <= next;
    end

    // Next-state logic (combinational)
    always @(*) begin
        case (state)
            S_IDLE : next = din ? S_1   : S_IDLE;
            S_1    : next = din ? S_1   : S_10;
            S_10   : next = din ? S_101 : S_IDLE;
            S_101  : next = din ? S_1   : S_10;
            default: next = S_IDLE;
        endcase
    end

    // Output depends ONLY on state -> Moore
    always @(*) begin
        detected = (state == S_101);
    end
endmodule

Mealy Machines: Outputs Depend on State AND Inputs

In a Mealy machine, the outputs depend on both the current state and the current inputs. This means an output can change the instant an input changes, even between clock edges. The machine reacts to what is happening right now, not just to which state it is sitting in.

The analogy: a Mealy machine is like a motion-sensor light. It responds immediately to movement in the room, rather than waiting for you to flip a switch on the wall.

Mealy machines usually need fewer states to do the same job, which can save flip-flops. The downside is that their outputs can glitch if the inputs are noisy, and they are a little harder to reason about during timing analysis. Here is the same “101” detector written in the Mealy style.

// Mealy FSM: detects the serial pattern "101"
module seq_detect_mealy (
    input  wire clk,
    input  wire rst,
    input  wire din,
    output reg  detected
);
    localparam S_IDLE = 2'b00; // seen nothing
    localparam S_1    = 2'b01; // seen "1"
    localparam S_10   = 2'b10; // seen "10"

    reg [1:0] state, next;

    // State register (sequential)
    always @(posedge clk) begin
        if (rst) state <= S_IDLE;
        else     state <= next;
    end

    // Next-state AND output depend on state + input -> Mealy
    always @(*) begin
        next     = state;
        detected = 1'b0;
        case (state)
            S_IDLE : next = din ? S_1 : S_IDLE;
            S_1    : next = din ? S_1 : S_10;
            S_10   : begin
                next     = din ? S_1 : S_IDLE;
                detected = din;   // asserts as the final "1" arrives
            end
            default: next = S_IDLE;
        endcase
    end
endmodule

Side-by-Side Comparison

The table below sums up the practical differences you will actually care about when you sit down to design.

                      Moore                 Mealy
---------------------------------------------------------------
Output depends on     State only            State + inputs
Reacts to an input    Next clock cycle      Same cycle (faster)
Output timing         Registered, clean     Combinational, can
                                            glitch
States needed         Usually more          Usually fewer
Ease of debugging     Easier                Harder
Beginner default      Yes                   Use with care

The Same Job, Two Ways

Both modules above detect the bit pattern 101 arriving serially on din. The interesting part is the timing of the detected signal:

• The Moore version raises detected for one full clock cycle after the pattern completes, and the output is registered and clean.
• The Mealy version raises detected the moment the final 1 arrives, one cycle earlier, but only while that input condition holds.

If you simulate both in your favorite tool, you will see the Mealy pulse land exactly one cycle before the Moore pulse. That single-cycle offset is the whole heart of the Moore versus Mealy distinction.

Which Should You Use?

For beginners, Moore machines are usually the safer default. Registered outputs mean fewer glitches, cleaner timing reports, and easier debugging. Most textbook designs, from traffic lights to counters to protocol controllers, are Moore machines for exactly this reason.

Reach for Mealy when you need to save states or must react to an input in the same cycle it arrives, such as in high-throughput datapaths or tight handshaking logic. Just be aware that you may need to register the Mealy output afterward to keep it clean, which ironically turns it back into something Moore-like.

In fact, a common professional pattern is the registered Mealy machine: compute the output with Mealy logic, then pass it through a single flip-flop. You get Mealy’s efficiency with Moore’s clean timing, which is the best of both worlds.

Common Beginner Pitfalls

• Forgetting to define the output for every state in a Moore machine, which can accidentally infer a latch.
• Letting a Mealy output depend on a glitchy combinational input, then wondering why downstream logic misbehaves.
• Mixing blocking and non-blocking assignments in the state register. Always use non-blocking assignments for sequential logic.

What’s Next

Now that you understand how FSM outputs are generated, the natural next step is state encoding: how the states themselves are represented in hardware. In the next article, we’ll explore One-Hot vs Binary Encoding in Verilog and see why that single choice can change how fast and how large your state machine becomes.

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